Commit e58e501a authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-3.19-iommu' of... 

Merge tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

Pull "ARM: tegra: IOMMU support for v3.19" from Thierry Reding:

This adds the driver pieces required for IOMMU support on Tegra30,
Tegra114 and Tegra124.

* tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  memory: Add NVIDIA Tegra memory controller support
  of: Add NVIDIA Tegra memory controller binding
  ARM: tegra: Move AHB Kconfig to drivers/amba
  amba: Add Kconfig file
  clk: tegra: Implement memory-controller clock
  powerpc/iommu: Rename iommu_[un]map_sg functions
  iommu: Improve error handling when setting bus iommu
  iommu: Do more input validation in iommu_map_sg()
  iommu: Add iommu_map_sg() function

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a8afa264 89184651

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt

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+36 −0
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NVIDIA Tegra Memory Controller device tree bindings

===================================================



Required properties:

- compatible: Should be "nvidia,tegra<chip>-mc"

- reg: Physical base address and length of the controller's registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts: The interrupt outputs from the controller.

- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines

  the SWGROUP of the master.



This device implements an IOMMU that complies with the generic IOMMU binding.

See ../iommu/iommu.txt for details.



Example:

--------



	mc: memory-controller@0,70019000 {

		compatible = "nvidia,tegra124-mc";

		reg = <0x0 0x70019000 0x0 0x1000>;

		clocks = <&tegra_car TEGRA124_CLK_MC>;

		clock-names = "mc";



		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;



		#iommu-cells = <1>;

	};



	sdhci@0,700b0000 {

		compatible = "nvidia,tegra124-sdhci";

		...

		iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;

	};

arch/arm/Kconfig

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@@ -1259,9 +1259,6 @@ source "arch/arm/common/Kconfig" 


menu "Bus support"



config ARM_AMBA

	bool



config ISA

	bool

	help

arch/arm/mach-tegra/Kconfig

+1 −8
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@@ -2,6 +2,7 @@ menuconfig ARCH_TEGRA 
	bool "NVIDIA Tegra" if ARCH_MULTI_V7

	select ARCH_REQUIRE_GPIOLIB

	select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS

	select ARM_AMBA

	select ARM_GIC

	select CLKSRC_MMIO

	select HAVE_ARM_SCU if SMP
@@ -59,12 +60,4 @@ config ARCH_TEGRA_124_SOC 
	  Support for NVIDIA Tegra T124 processor family, based on the

	  ARM CortexA15MP CPU



config TEGRA_AHB

	bool "Enable AHB driver for NVIDIA Tegra SoCs"

	default y

	help

	  Adds AHB configuration functionality for NVIDIA Tegra SoCs,

	  which controls AHB bus master arbitration and some

	  performance parameters(priority, prefech size).



endif

arch/arm64/Kconfig

+0 −3
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@@ -166,9 +166,6 @@ endmenu 


menu "Bus support"



config ARM_AMBA

	bool



config PCI

	bool "PCI support"

	help

arch/powerpc/include/asm/iommu.h

+10 −7
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@@ -137,12 +137,15 @@ static inline void set_iommu_table_base_and_group(struct device *dev, 
	iommu_add_device(dev);

}



extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,

extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,

			    struct scatterlist *sglist, int nelems,

			unsigned long mask, enum dma_data_direction direction,

			    unsigned long mask,

			    enum dma_data_direction direction,

			    struct dma_attrs *attrs);

extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,

			   int nelems, enum dma_data_direction direction,

extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,

			       struct scatterlist *sglist,

			       int nelems,

			       enum dma_data_direction direction,

			       struct dma_attrs *attrs);



extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,

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