Commit e444d51b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'tty-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 

Pull tty/serial driver updates from Greg KH:
 "Even in this age, people are still making new serial port silicon,
  why...

  Anyway, here's the TTY and Serial driver update for 5.4-rc1. Lots of
  changes in here for a number of embedded serial port devices that are
  being worked on because people really like to see those console
  logs...

  Other than that, nothing major here, no core tty changes that anyone
  should care about.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'tty-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (125 commits)
  serial: tegra: Add PIO mode support
  serial: tegra: report clk rate errors
  serial: tegra: add support to adjust baud rate
  serial: tegra: DT for Adjusted baud rates
  serial: tegra: add support to use 8 bytes trigger
  serial: tegra: set maximum num of uart ports to 8
  serial: tegra: check for FIFO mode enabled status
  dt-binding: serial: tegra: add new chips
  serial: tegra: report error to upper tty layer
  serial: tegra: flush the RX fifo on frame error
  serial: tegra: avoid reg access when clk disabled
  serial: tegra: add support to ignore read
  serial: sprd: correct the wrong sequence of arguments
  dt-bindings: serial: Convert riscv,sifive-serial to json-schema
  serial: max310x: turn off transmitter before activating AutoCTS or auto transmitter flow control
  serial: max310x: Properly set flags in AutoCTS mode
  tty: serial: fix platform_no_drv_owner.cocci warnings
  dt-bindings: serial: Document Freescale LINFlexD UART
  serial: fsl_linflexuart: Update compatible string
  tty: n_gsm: avoid recursive locking with async port hangup
  ...
parents c6b48dad 1dce2df3

Documentation/admin-guide/kernel-parameters.txt

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@@ -1094,6 +1094,12 @@ 
			the framebuffer, pass the 'ram' option so that it is

			mapped with the correct attributes.



		linflex,<addr>

			Use early console provided by Freescale LinFlex UART

			serial driver for NXP S32V234 SoCs. A valid base

			address must be provided, and the serial port must

			already be setup and configured.



	earlyprintk=	[X86,SH,ARM,M68k,S390]

			earlyprintk=vga

			earlyprintk=sclp

Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt

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* Freescale LINFlexD UART



The LINFlexD controller implements several LIN protocol versions, as well as

support for full-duplex UART communication through 8-bit and 9-bit frames.



See chapter 47 ("LINFlexD") in the reference manual[1].



Required properties:

- compatible :

  - "fsl,s32v234-linflexuart" for LINFlexD configured in UART mode, which

    is compatible with the one integrated on S32V234 SoC

- reg : Address and length of the register set for the device

- interrupts : Should contain uart interrupt



Example:

uart0: serial@40053000 {

	compatible = "fsl,s32v234-linflexuart";

	reg = <0x0 0x40053000 0x0 0x1000>;

	interrupts = <0 59 4>;

};



[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM

Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt

+38 −1
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NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.



Required properties:

- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".

- compatible : should be,

  "nvidia,tegra20-hsuart" for Tegra20,

  "nvidia,tegra30-hsuart" for Tegra30,

  "nvidia,tegra186-hsuart" for Tegra186,

  "nvidia,tegra194-hsuart" for Tegra194.



- reg: Should contain UART controller registers location and length.

- interrupts: Should contain UART controller interrupts.

- clocks: Must contain one entry, for the module clock.
@@ -19,6 +24,37 @@ Required properties: 
Optional properties:

- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable

		only if all 8 lines of UART controller are pinmuxed.

- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate

  adjustment within a range.

  Each entry contains sets of 3 values. Range low/high and adjusted rate.

  <range_low range_high adjusted_rate>

  When baud rate set on controller falls within the range mentioned in this

  field, baud rate will be adjusted by percentage mentioned here.

  Ex: <9600 115200 200>

  Increase baud rate by 2% when set baud rate falls within range 9600 to 115200



Baud Rate tolerance:

  Standard UART devices are expected to have tolerance for baud rate error by

  -4 to +4 %. All Tegra devices till Tegra210 had this support. However,

  Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level

  is 0% to +4% in 1-stop config. Otherwise, the received data will have

  corruption/invalid framing errors. Parker errata suggests adjusting baud

  rate to be higher than the deviations observed in Tx.



  Tx deviation of connected device can be captured over scope (or noted from

  its spec) for valid range and Tegra baud rate has to be set above actual

  Tx baud rate observed. To do this we use nvidia,adjust-baud-rates



  As an example, consider there is deviation observed in Tx for baud rates as

  listed below.

  0 to 9600 has 1% deviation

  9600 to 115200 2% deviation

  This slight deviation is expcted and Tegra UART is expected to handle it. Due

  to the issue stated above, baud rate on Tegra UART should be set equal to or

  above deviation observed for avoiding frame errors.

  Property should be set like this

  nvidia,adjust-baud-rates = <0 9600 100>,

  			     <9600 115200 200>;



Example:
@@ -33,4 +69,5 @@ serial@70006000 { 
	reset-names = "serial";

	dmas = <&apbdma 8>, <&apbdma 8>;

	dma-names = "rx", "tx";

	nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */

};

Documentation/devicetree/bindings/serial/sifive-serial.txt

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SiFive asynchronous serial interface (UART)



Required properties:



- compatible: should be something similar to

	      "sifive,<chip>-uart" for the UART as integrated

	      on a particular chip, and "sifive,uart<version>" for the

	      general UART IP block programming model.	Supported

	      compatible strings as of the date of this writing are:

	      "sifive,fu540-c000-uart" for the SiFive UART v0 as

	      integrated onto the SiFive FU540 chip, or "sifive,uart0"

	      for the SiFive UART v0 IP block with no chip integration

	      tweaks (if any)

- reg: address and length of the register space

- interrupts: Should contain the UART interrupt identifier

- clocks: Should contain a clock identifier for the UART's parent clock





UART HDL that corresponds to the IP block version numbers can be found

here:



https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart





Example:



uart0: serial@10010000 {

	compatible = "sifive,fu540-c000-uart", "sifive,uart0";

	interrupt-parent = <&plic0>;

	interrupts = <80>;

	reg = <0x0 0x10010000 0x0 0x1000>;

	clocks = <&prci PRCI_CLK_TLCLK>;

};

Documentation/devicetree/bindings/serial/sifive-serial.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/serial/sifive-serial.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SiFive asynchronous serial interface (UART)



maintainers:

  - Pragnesh Patel <pragnesh.patel@sifive.com>

  - Paul Walmsley  <paul.walmsley@sifive.com>

  - Palmer Dabbelt <palmer@sifive.com>



allOf:

  - $ref: /schemas/serial.yaml#



properties:

  compatible:

    items:

      - const: sifive,fu540-c000-uart

      - const: sifive,uart0



    description:

      Should be something similar to "sifive,<chip>-uart"

      for the UART as integrated on a particular chip,

      and "sifive,uart<version>" for the general UART IP

      block programming model.



      UART HDL that corresponds to the IP block version

      numbers can be found here -



      https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks



additionalProperties: false



examples:

  - |

      #include <dt-bindings/clock/sifive-fu540-prci.h>

      serial@10010000 {

        compatible = "sifive,fu540-c000-uart", "sifive,uart0";

        interrupt-parent = <&plic0>;

        interrupts = <80>;

        reg = <0x0 0x10010000 0x0 0x1000>;

        clocks = <&prci PRCI_CLK_TLCLK>;

      };



...

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