Commit c6b48dad authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull USB updates from Greg KH:
 "Here is the big set of USB patches for 5.4-rc1.

  Two major chunks of code are moving out of the tree and into the
  staging directory, uwb and wusb (wireless USB support), because there
  are no devices that actually use this protocol anymore, and what we
  have today probably doesn't work at all given that the maintainers
  left many many years ago. So move it to staging where it will be
  removed in a few releases if no one screams.

  Other than that, lots of little things. The usual gadget and xhci and
  usb serial driver updates, along with a bunch of sysfs file cleanups
  due to the driver core changes to support that. Nothing really major,
  just constant forward progress.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (159 commits)
  USB: usbcore: Fix slab-out-of-bounds bug during device reset
  usb: cdns3: Remove redundant dev_err call in cdns3_probe()
  USB: rio500: Fix lockdep violation
  USB: rio500: simplify locking
  usb: mtu3: register a USB Role Switch for dual role mode
  usb: common: add USB GPIO based connection detection driver
  usb: common: create Kconfig file
  usb: roles: get usb-role-switch from parent
  usb: roles: Add fwnode_usb_role_switch_get() function
  device connection: Add fwnode_connection_find_match()
  usb: roles: Introduce stubs for the exiting functions in role.h
  dt-bindings: usb: mtu3: add properties about USB Role Switch
  dt-bindings: usb: add binding for USB GPIO based connection detection driver
  dt-bindings: connector: add optional properties for Type-B
  dt-binding: usb: add usb-role-switch property
  usbip: Implement SG support to vhci-hcd and stub driver
  usb: roles: intel: Enable static DRD mode for role switch
  xhci-ext-caps.c: Add property to disable Intel SW switch
  usb: dwc3: remove generic PHY calibrate() calls
  usb: core: phy: add support for PHY calibration
  ...
parents 1f7d290a fb9617ed
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+14 −0
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@@ -17,6 +17,20 @@ Optional properties:
- self-powered: Set this property if the usb device that has its own power
  source.

Optional properties for usb-b-connector:
- id-gpios: an input gpio for USB ID pin.
- vbus-gpios: an input gpio for USB VBUS pin, used to detect presence of
  VBUS 5V.
  see gpio/gpio.txt.
- vbus-supply: a phandle to the regulator for USB VBUS if needed when host
  mode or dual role mode is supported.
  Particularly, if use an output GPIO to control a VBUS regulator, should
  model it as a regulator.
  see regulator/fixed-regulator.yaml
- pinctrl-names : a pinctrl state named "default" is optional
- pinctrl-0 : pin control group
  see pinctrl/pinctrl-bindings.txt

Optional properties for usb-c-connector:
- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
  connector has power support.
+45 −0
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Binding for the Cadence USBSS-DRD controller

Required properties:
 - reg: Physical base address and size of the controller's register areas.
	 Controller has 3 different regions:
	 - HOST registers area
	 - DEVICE registers area
	 - OTG/DRD registers area
 - reg-names - register memory area names:
	"xhci" - for HOST registers space
	"dev" - for DEVICE registers space
	"otg" - for OTG/DRD registers space
 - compatible: Should contain: "cdns,usb3"
 - interrupts: Interrupts used by cdns3 controller:
	"host" - interrupt used by XHCI driver.
	"peripheral" - interrupt used by device driver
	"otg" - interrupt used by DRD/OTG  part of driver

Optional properties:
 - maximum-speed : valid arguments are "super-speed", "high-speed" and
                   "full-speed"; refer to usb/generic.txt
 - dr_mode: Should be one of "host", "peripheral" or "otg".
 - phys: reference to the USB PHY
 - phy-names: from the *Generic PHY* bindings;
	Supported names are:
	- cdns3,usb2-phy
	- cdns3,usb3-phy

 - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints
	buffers expressed in KB

Example:
	usb@f3000000 {
		compatible = "cdns,usb3";
		interrupts = <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_USB_IRQ  7 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_USB_IRQ  8 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "host", "peripheral", "otg";
		reg = <0xf3000000 0x10000>,	/* memory area for HOST registers */
			<0xf3010000 0x10000>,	/* memory area for DEVICE registers */
			<0xf3020000 0x10000>;	/* memory area for OTG/DRD registers */
		reg-names = "xhci", "dev", "otg";
		phys = <&usb2_phy>, <&usb3_phy>;
		phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy";
	};
+1 −0
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@@ -10,6 +10,7 @@ Required properties:
	"fsl,imx6sx-usb"
	"fsl,imx6ul-usb"
	"fsl,imx7d-usb"
	"fsl,imx7ulp-usb"
	"lsi,zevio-usb"
	"qcom,ci-hdrc"
	"chipidea,usb2"
+14 −27
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@@ -12,13 +12,11 @@ Required properties:
 - interrupts: interrupt number to the cpu.
 - clocks: from common clock binding: handle to usb clock.
 - clock-names: from common clock binding: Shall be "usbhost".
 - port: if in the SoC there are EHCI phys, they should be listed here.
   One phy per port. Each port should have following entries:
	- reg: port number on EHCI controller, e.g
	       On Exynos5250, port 0 is USB2.0 otg phy
			      port 1 is HSIC phy0
			      port 2 is HSIC phy1
	- phys: from the *Generic PHY* bindings; specifying phy used by port.
 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
   by the root port.
 - phy-names: from the *Generic PHY* bindings; array of the names for
   each phy for the root ports, must be a subset of the following:
   "host", "hsic0", "hsic1".

Optional properties:
 - samsung,vbus-gpio:  if present, specifies the GPIO that
@@ -35,12 +33,8 @@ Example:
		clocks = <&clock 285>;
		clock-names = "usbhost";

		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		    reg = <0>;
		phys = <&usb2phy 1>;
		};
		phy-names = "host";
	};

OHCI
@@ -52,13 +46,11 @@ Required properties:
 - interrupts: interrupt number to the cpu.
 - clocks: from common clock binding: handle to usb clock.
 - clock-names: from common clock binding: Shall be "usbhost".
 - port: if in the SoC there are OHCI phys, they should be listed here.
   One phy per port. Each port should have following entries:
	- reg: port number on OHCI controller, e.g
	       On Exynos5250, port 0 is USB2.0 otg phy
			      port 1 is HSIC phy0
			      port 2 is HSIC phy1
	- phys: from the *Generic PHY* bindings, specifying phy used by port.
 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
   by the root port.
 - phy-names: from the *Generic PHY* bindings; array of the names for
   each phy for the root ports, must be a subset of the following:
   "host", "hsic0", "hsic1".

Example:
	usb@12120000 {
@@ -69,13 +61,8 @@ Example:
		clocks = <&clock 285>;
		clock-names = "usbhost";

		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		    reg = <0>;
		phys = <&usb2phy 1>;
		};

		phy-names = "host";
	};

DWC3
+0 −7
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@@ -11,13 +11,6 @@ Required sub-node:

	Documentation/devicetree/bindings/connector/usb-connector.txt

Deprecated properties :
- fcs,max-sink-microvolt : Maximum sink voltage accepted by port controller
- fcs,max-sink-microamp : Maximum sink current accepted by port controller
- fcs,max-sink-microwatt : Maximum sink power accepted by port controller
- fcs,operating-sink-microwatt : Minimum amount of power accepted from a sink
  when negotiating


Example:

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