Merge tag 'pci-v5.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci (e2557a2c) · Commits · 戴 / test

drivers/pci/controller/dwc/pcie-designware-host.c

+6 −2

Original line number	Diff line number	Diff line
		@@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
		* ATU, so we should not program the ATU here.
		*/
		if (pp->bridge->child_ops == &dw_child_pcie_ops) {
		struct resource_entry *entry =
		resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
		struct resource_entry tmp, entry = NULL;

		/* Get last memory resource entry */
		resource_list_for_each_entry(tmp, &pp->bridge->windows)
		if (resource_type(tmp->res) == IORESOURCE_MEM)
		entry = tmp;

		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
		PCIE_ATU_TYPE_MEM, entry->res->start,

drivers/pci/controller/pci-mvebu.c

+10 −13

Original line number	Diff line number	Diff line
		@@ -958,25 +958,16 @@ static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
		}

		/*
		* We can't use devm_of_pci_get_host_bridge_resources() because we
		* need to parse our special DT properties encoding the MEM and IO
		* apertures.
		* devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
		* so we need extra resource setup parsing our special DT properties encoding
		* the MEM and IO apertures.
		*/
		static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
		{
		struct device *dev = &pcie->pdev->dev;
		struct device_node *np = dev->of_node;
		struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
		int ret;

		/* Get the bus range */
		ret = of_pci_parse_bus_range(np, &pcie->busn);
		if (ret) {
		dev_err(dev, "failed to parse bus-range property: %d\n", ret);
		return ret;
		}
		pci_add_resource(&bridge->windows, &pcie->busn);

		/* Get the PCIe memory aperture */
		mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
		if (resource_size(&pcie->mem) == 0) {
		@@ -986,6 +977,9 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)

		pcie->mem.name = "PCI MEM";
		pci_add_resource(&bridge->windows, &pcie->mem);
		ret = devm_request_resource(dev, &iomem_resource, &pcie->mem);
		if (ret)
		return ret;

		/* Get the PCIe IO aperture */
		mvebu_mbus_get_pcie_io_aperture(&pcie->io);
		@@ -999,9 +993,12 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
		pcie->realio.name = "PCI I/O";

		pci_add_resource(&bridge->windows, &pcie->realio);
		ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
		if (ret)
		return ret;
		}

		return devm_request_pci_bus_resources(dev, &bridge->windows);
		return 0;
		}

		/*

drivers/pci/pci.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -3516,7 +3516,12 @@ void pci_acs_init(struct pci_dev *dev)
		{
		dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);

		if (dev->acs_cap)
		/*
		* Attempt to enable ACS regardless of capability because some Root
		* Ports (e.g. those quirked with _intel_pch_acs_) do not have
		* the standard ACS capability but still support ACS via those
		* quirks.
		*/
		pci_enable_acs(dev);
		}

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