Commit 4ef8451b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-for-v5.10-2020-11-03' of... 

Merge tag 'perf-tools-for-v5.10-2020-11-03' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

Pull perf tools fixes from Arnaldo Carvalho de Melo:
 "Only fixes and a sync of the headers so that the perf build is silent:

   - Fix visibility attribute in python module init code with newer gcc

   - Fix DRAM_BW_Use 0 issue for CLX/SKX in intel JSON vendor event
     files

   - Fix the build on new fedora by removing LTO compiler options when
     building perl support

   - Remove broken __no_tail_call attribute

   - Fix segfault when trying to trace events by cgroup

   - Fix crash with non-jited BPF progs

   - Increase buffer size in TUI browser, fixing format truncation

   - Fix printing of build-id for objects lacking one

   - Fix byte swapping for ino_generation field in MMAP2 perf.data
     records

   - Fix byte swapping for CGROUP perf.data records, for cross arch
     analysis of perf.data files

   - Fix the fast path of feature detection

   - Update kernel header copies"

* tag 'perf-tools-for-v5.10-2020-11-03' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (23 commits)
  tools feature: Fixup fast path feature detection
  perf tools: Add missing swap for cgroup events
  perf tools: Add missing swap for ino_generation
  perf tools: Initialize output buffer in build_id__sprintf
  perf hists browser: Increase size of 'buf' in perf_evsel__hists_browse()
  tools include UAPI: Update linux/mount.h copy
  tools headers UAPI: Update tools's copy of linux/perf_event.h
  tools kvm headers: Update KVM headers from the kernel sources
  tools UAPI: Update copy of linux/mman.h from the kernel sources
  tools arch x86: Sync the msr-index.h copy with the kernel sources
  tools x86 headers: Update required-features.h header from the kernel
  tools x86 headers: Update cpufeatures.h headers copies
  tools headers UAPI: Update fscrypt.h copy
  tools headers UAPI: Sync drm/i915_drm.h with the kernel sources
  tools headers UAPI: Sync prctl.h with the kernel sources
  perf scripting python: Avoid declaring function pointers with a visibility attribute
  perf tools: Remove broken __no_tail_call attribute
  perf vendor events: Fix DRAM_BW_Use 0 issue for CLX/SKX
  perf trace: Fix segfault when trying to trace events by cgroup
  perf tools: Fix crash with non-jited bpf progs
  ...
parents e6b0bd61 5d020cbd

tools/arch/arm64/include/uapi/asm/kvm.h

+25 −0
Original line number Diff line number Diff line
@@ -159,6 +159,21 @@ struct kvm_sync_regs { 
struct kvm_arch_memory_slot {

};



/*

 * PMU filter structure. Describe a range of events with a particular

 * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.

 */

struct kvm_pmu_event_filter {

	__u16	base_event;

	__u16	nevents;



#define KVM_PMU_EVENT_ALLOW	0

#define KVM_PMU_EVENT_DENY	1



	__u8	action;

	__u8	pad[3];

};



/* for KVM_GET/SET_VCPU_EVENTS */

struct kvm_vcpu_events {

	struct {
@@ -242,6 +257,15 @@ struct kvm_vcpu_events { 
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2



/*

 * Only two states can be presented by the host kernel:

 * - NOT_REQUIRED: the guest doesn't need to do anything

 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)

 *

 * All the other values are deprecated. The host still accepts all

 * values (they are ABI), but will narrow them to the above two.

 */

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
@@ -329,6 +353,7 @@ struct kvm_vcpu_events { 
#define KVM_ARM_VCPU_PMU_V3_CTRL	0

#define   KVM_ARM_VCPU_PMU_V3_IRQ	0

#define   KVM_ARM_VCPU_PMU_V3_INIT	1

#define   KVM_ARM_VCPU_PMU_V3_FILTER	2

#define KVM_ARM_VCPU_TIMER_CTRL		1

#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0

#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1

tools/arch/s390/include/uapi/asm/sie.h

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
	{ 0x13, "SIGP conditional emergency signal" },		\

	{ 0x15, "SIGP sense running" },				\

	{ 0x16, "SIGP set multithreading"},			\

	{ 0x17, "SIGP store additional status ait address"}

	{ 0x17, "SIGP store additional status at address"}



#define icpt_prog_codes						\

	{ 0x0001, "Prog Operation" },				\

tools/arch/x86/include/asm/cpufeatures.h

+5 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ 
#define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */

#define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */

/* free					( 3*32+17) */

#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */

#define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */

#define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */

#define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
@@ -236,6 +236,7 @@ 
#define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */

#define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */

#define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */

#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */

#define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
@@ -288,6 +289,7 @@ 
#define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */

#define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */

#define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */

#define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
@@ -353,6 +355,7 @@ 
#define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */

#define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */

#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */

#define X86_FEATURE_ENQCMD		(16*32+29) /* ENQCMD and ENQCMDS instructions */



/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */

#define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
@@ -368,6 +371,7 @@ 
#define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */

#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */

#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */

#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

tools/arch/x86/include/asm/disabled-features.h

+8 −1
Original line number Diff line number Diff line
@@ -56,6 +56,12 @@ 
# define DISABLE_PTI		(1 << (X86_FEATURE_PTI & 31))

#endif



#ifdef CONFIG_IOMMU_SUPPORT

# define DISABLE_ENQCMD	0

#else

# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))

#endif



/*

 * Make sure to add features to the correct mask

 */
@@ -75,7 +81,8 @@ 
#define DISABLED_MASK13	0

#define DISABLED_MASK14	0

#define DISABLED_MASK15	0

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \

			 DISABLE_ENQCMD)

#define DISABLED_MASK17	0

#define DISABLED_MASK18	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

tools/arch/x86/include/asm/msr-index.h

+10 −0
Original line number Diff line number Diff line
@@ -257,6 +257,9 @@ 
#define MSR_IA32_LASTINTFROMIP		0x000001dd

#define MSR_IA32_LASTINTTOIP		0x000001de



#define MSR_IA32_PASID			0x00000d93

#define MSR_IA32_PASID_VALID		BIT_ULL(31)



/* DEBUGCTLMSR bits (others vary by model): */

#define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */

#define DEBUGCTLMSR_BTF_SHIFT		1
@@ -464,11 +467,15 @@ 
#define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)

#define MSR_AMD64_IBSCTL		0xc001103a

#define MSR_AMD64_IBSBRTARGET		0xc001103b

#define MSR_AMD64_ICIBSEXTDCTL		0xc001103c

#define MSR_AMD64_IBSOPDATA4		0xc001103d

#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */

#define MSR_AMD64_SEV_ES_GHCB		0xc0010130

#define MSR_AMD64_SEV			0xc0010131

#define MSR_AMD64_SEV_ENABLED_BIT	0

#define MSR_AMD64_SEV_ES_ENABLED_BIT	1

#define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)

#define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)



#define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
@@ -857,11 +864,14 @@ 
#define MSR_CORE_PERF_FIXED_CTR0	0x00000309

#define MSR_CORE_PERF_FIXED_CTR1	0x0000030a

#define MSR_CORE_PERF_FIXED_CTR2	0x0000030b

#define MSR_CORE_PERF_FIXED_CTR3	0x0000030c

#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d

#define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e

#define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f

#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390



#define MSR_PERF_METRICS		0x00000329



/* PERF_GLOBAL_OVF_CTL bits */

#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55

#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)

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