Commit e17a512a authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu: RLC must be disabled after SMU when S3 on navi 



SMU requires to interact with RLC when disable all features,
so RLC shouldn't be disabled ahead of SMU.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2a8bfa13

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −3
Original line number Diff line number Diff line
@@ -1573,8 +1573,6 @@ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 


	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);



	gfx_v10_0_enable_gui_idle_interrupt(adev, false);

}



static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
@@ -3607,7 +3605,7 @@ static int gfx_v10_0_hw_fini(void *handle) 
		return 0;

	}

	gfx_v10_0_cp_enable(adev, false);

	gfx_v10_0_rlc_stop(adev);

	gfx_v10_0_enable_gui_idle_interrupt(adev, false);



	return 0;

}

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+4 −0
Original line number Diff line number Diff line
@@ -943,6 +943,10 @@ static int smu_suspend(void *handle) 


	smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);



	if (adev->asic_type >= CHIP_NAVI10 &&

	    adev->gfx.rlc.funcs->stop)

		adev->gfx.rlc.funcs->stop(adev);



	return 0;

}

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