Commit e15d598b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.20' of... 

Merge tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull allwinner clock changes from Maxime Ripard:

Our usual set of changes for the Allwinner SoCs clock support.

The most notable changes are:
  - A bunch of changes and fixes to support the A64 display engine
  - Some fixes to support the A83t display engine

* tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
  clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
  clk: sunxi-ng: a64: Add minimal rate for video PLLs
  clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
  clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
  clk: sunxi-ng: nkmp: Add constraint for maximum rate
  clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
  clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
  clk: sunxi-ng: Add maximum rate constraint to NM PLLs
  clk: sunxi-ng: h6: fix PWM gate/reset offset
  clk: sunxi-ng: h6: fix bus clocks' divider position
parents 5b394b2d 8b2a3787

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+26 −22
Original line number Diff line number Diff line
@@ -64,8 +64,10 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 
				   BIT(28),	/* lock */

				   CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",

						"osc24M", 0x010,

						192000000,	/* Minimum rate */

						1008000000,	/* Maximum rate */

						8, 7,		/* N */

						0, 4,		/* M */

						BIT(24),	/* frac enable */
@@ -125,8 +127,10 @@ static struct ccu_nk pll_periph1_clk = { 
	},

};



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",

						"osc24M", 0x030,

						192000000,	/* Minimum rate */

						1008000000,	/* Maximum rate */

						8, 7,		/* N */

						0, 4,		/* M */

						BIT(24),	/* frac enable */

drivers/clk/sunxi-ng/ccu-sun50i-a64.h

+3 −1
Original line number Diff line number Diff line
@@ -27,7 +27,9 @@ 
#define CLK_PLL_AUDIO_2X		4

#define CLK_PLL_AUDIO_4X		5

#define CLK_PLL_AUDIO_8X		6

#define CLK_PLL_VIDEO0			7



/* PLL_VIDEO0 exported for HDMI PHY */



#define CLK_PLL_VIDEO0_2X		8

#define CLK_PLL_VE			9

#define CLK_PLL_DDR0			10

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+28 −25
Original line number Diff line number Diff line
@@ -224,7 +224,7 @@ static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", 
			     psi_ahb1_ahb2_parents,

			     0x510,

			     0, 5,	/* M */

			     16, 2,	/* P */

			     8, 2,	/* P */

			     24, 2,	/* mux */

			     0);
@@ -233,19 +233,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", 
						       "pll-periph0" };

static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,

			     0, 5,	/* M */

			     16, 2,	/* P */

			     8, 2,	/* P */

			     24, 2,	/* mux */

			     0);



static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,

			     0, 5,	/* M */

			     16, 2,	/* P */

			     8, 2,	/* P */

			     24, 2,	/* mux */

			     0);



static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,

			     0, 5,	/* M */

			     16, 2,	/* P */

			     8, 2,	/* P */

			     24, 2,	/* mux */

			     0);
@@ -352,7 +352,7 @@ static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", 
static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",

		      0x79c, BIT(0), 0);



static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x79c, BIT(0), 0);

static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);



static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
@@ -408,25 +408,28 @@ static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); 


static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",

					    "pll-periph1-2x" };

static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_parents, 0x830,

static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,

					  0, 4,		/* M */

					  8, 2,		/* N */

					  24, 3,	/* mux */

					  BIT(31),	/* gate */

					  2,		/* post-div */

					  0);



static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_parents, 0x834,

static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,

					  0, 4,		/* M */

					  8, 2,		/* N */

					  24, 3,	/* mux */

					  BIT(31),	/* gate */

					  2,		/* post-div */

					  0);



static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_parents, 0x838,

static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,

					  0, 4,		/* M */

					  8, 2,		/* N */

					  24, 3,	/* mux */

					  BIT(31),	/* gate */

					  2,		/* post-div */

					  0);



static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+2 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ static struct ccu_nkmp pll_video0_clk = { 
	.n		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),

	.m		= _SUNXI_CCU_DIV(16, 1), /* input divider */

	.p		= _SUNXI_CCU_DIV(0, 2), /* output divider */

	.max_rate	= 3000000000UL,

	.common		= {

		.reg		= 0x010,

		.lock_reg	= CCU_SUN8I_A83T_LOCK_REG,
@@ -220,6 +221,7 @@ static struct ccu_nkmp pll_video1_clk = { 
	.n		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),

	.m		= _SUNXI_CCU_DIV(16, 1), /* input divider */

	.p		= _SUNXI_CCU_DIV(0, 2), /* external divider p */

	.max_rate	= 3000000000UL,

	.common		= {

		.reg		= 0x04c,

		.lock_reg	= CCU_SUN8I_A83T_LOCK_REG,

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+13 −12
Original line number Diff line number Diff line
@@ -69,9 +69,10 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 
				       BIT(28),	/* lock */

				       CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",

						"osc24M", 0x0010,

						192000000, /* Minimum rate */

						912000000, /* Maximum rate */

						8, 7,      /* N */

						0, 4,	   /* M */

						BIT(24),   /* frac enable */

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