Commit e0a3def2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2019-03-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



UAPI Changes:
- Make mmap code more asynchronous. Avoid full SET_DOMAIN on GTT mmap pagefault,
  and flushes pages on acquisition instead. Moves some of the work from mmap fault
  time to execbuf time to avoid lock contention during mmap access.

  Has neutral to positive impact on perf as the flushing moves to execbuf time
  in real world workloads on the current known userspaces due to recycling of BOs.

  If there exist an unknown non-recycling userspace, they should explicitly do the
  SET_DOMAIN and not rely on kernel doing implicit SET_DOMAIN because swapout/in
  might have happenedt.

- Restore the accidentally removed behaviour of returning object size on GEM_CREATE
  From 2011: ff72145b ("drm: dumb scanout create/mmap for intel/radeon (v3)")

- Includes a some neutered patches to prepare to complete the earlier Mesa
  recovery feature uAPI. Looking to enable this in the next PR.

Driver Changes:

- Add Elkhartlake (Gen11) support code and PCI IDs
- Add missing Amberlake PCI ID 0x87CA (Ville)
- Fix to Bugzilla #109780: Pick the first mode from EDID as the fixed mode when there is no preferred mode (Ville)
- Fix GCC 4.8 build by using __is_constexpr() (Chris, Randy, Uma)
- Add "Broadcast RGB", "force_audio" and "max_bpc" properties to DP MST (Ville)
- Remove 8bpc limitation from DP MST (Ville)
- Fix changing between limited and full range RGB output in DP fastsets (Ville)
- Reject unsupported HDR formats (Maarten)
- Handle YUV subpixel support better (Maarten)

- Various plane watermarks fixes and cleaning of the code (Ville)
- Icelake port sync master select fix (Manasi)
- Icelake VEBOX disable bitmask fix (Jose)
- Close a race where userspace could see incompletely initialized GEM context (Chris)
- Avoid C3 on i945gm to keep vblank interrupts steady (Ville)
- Avoid recalculating PLL HW readout each time (Lucas)
- A ton of patches to modularize uncore code (Daniel)

- Instead of storing media fuse value, immediately derive engine masks (Daniele)
- Reduce struct_mutex usage (Chris)
- Iterate over child devices to initialize ddi_port_info (Jani)
- Fixes to return correct error values when bailing out of functions (Dan)
- Use bitmap_zalloc() (Andy)
- Reorder and clarify Gen3/4 code (Ville)
- Refactor out common code in display mode handling (Ville)
- GuC code fixes (Sujaritha, Michal)
- Selftest improvements (Chris)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190328151515.GA9606@jlahtine-desk.ger.corp.intel.com
parents f144e67b a01b2c6f

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ i915-y := i915_drv.o \ 
	  i915_sw_fence.o \

	  i915_syncmap.o \

	  i915_sysfs.o \

	  i915_user_extensions.o \

	  intel_csr.o \

	  intel_device_info.o \

	  intel_pm.o \

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Diff line number Diff line
@@ -1848,7 +1848,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);



	MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);

	MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);

	MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);

	MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);

	MMIO_D(GEN7_CXT_SIZE, D_ALL);

drivers/gpu/drm/i915/gvt/mmio_context.c

+8 −7
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ out: 
static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_vgpu_submission *s = &vgpu->submission;

	enum forcewake_domains fw;

	i915_reg_t reg;
@@ -351,21 +352,21 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 
	 * otherwise device can go to RC6 state and interrupt invalidation

	 * process

	 */

	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,

	fw = intel_uncore_forcewake_for_reg(uncore, reg,

					    FW_REG_READ | FW_REG_WRITE);

	if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)

		fw |= FORCEWAKE_RENDER;



	intel_uncore_forcewake_get(dev_priv, fw);

	intel_uncore_forcewake_get(uncore, fw);



	I915_WRITE_FW(reg, 0x1);

	intel_uncore_write_fw(uncore, reg, 0x1);



	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))

	if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50))

		gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);

	else

		vgpu_vreg_t(vgpu, reg) = 0;



	intel_uncore_forcewake_put(dev_priv, fw);

	intel_uncore_forcewake_put(uncore, fw);



	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);

}
@@ -552,9 +553,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, 
	 * performace for batch mmio read/write, so we need

	 * handle forcewake mannually.

	 */

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);

	switch_mmio(pre, next, ring_id);

	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);

}



/**

drivers/gpu/drm/i915/gvt/scheduler.c

+2 −2
Original line number Diff line number Diff line
@@ -988,7 +988,7 @@ static int workload_thread(void *priv) 
				workload->ring_id, workload);



		if (need_force_wake)

			intel_uncore_forcewake_get(gvt->dev_priv,

			intel_uncore_forcewake_get(&gvt->dev_priv->uncore,

					FORCEWAKE_ALL);



		ret = dispatch_workload(workload);
@@ -1010,7 +1010,7 @@ complete: 
		complete_current_workload(gvt, ring_id);



		if (need_force_wake)

			intel_uncore_forcewake_put(gvt->dev_priv,

			intel_uncore_forcewake_put(&gvt->dev_priv->uncore,

					FORCEWAKE_ALL);



		intel_runtime_pm_put_unchecked(gvt->dev_priv);

drivers/gpu/drm/i915/i915_debugfs.c

+12 −12
Original line number Diff line number Diff line
@@ -409,9 +409,8 @@ static void print_context_stats(struct seq_file *m, 


			rcu_read_lock();

			task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);

			snprintf(name, sizeof(name), "%s/%d",

				 task ? task->comm : "<unknown>",

				 ctx->user_handle);

			snprintf(name, sizeof(name), "%s",

				 task ? task->comm : "<unknown>");

			rcu_read_unlock();



			print_file_stats(m, name, stats);
@@ -881,7 +880,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
		for_each_engine(engine, dev_priv, id) {

			seq_printf(m,

				   "Graphics Interrupt mask (%s):	%08x\n",

				   engine->name, I915_READ_IMR(engine));

				   engine->name, ENGINE_READ(engine, RING_IMR));

		}

	}
@@ -1094,7 +1093,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		}



		/* RPSTAT1 is in the GT power well */

		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);



		reqf = I915_READ(GEN6_RPNSWREQ);

		if (INTEL_GEN(dev_priv) >= 9)
@@ -1122,7 +1121,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		cagf = intel_gpu_freq(dev_priv,

				      intel_get_cagf(dev_priv, rpstat));



		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);



		if (INTEL_GEN(dev_priv) >= 11) {

			pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
@@ -1414,13 +1413,14 @@ static int ironlake_drpc_info(struct seq_file *m) 
static int i915_forcewake_domains(struct seq_file *m, void *data)

{

	struct drm_i915_private *i915 = node_to_i915(m->private);

	struct intel_uncore *uncore = &i915->uncore;

	struct intel_uncore_forcewake_domain *fw_domain;

	unsigned int tmp;



	seq_printf(m, "user.bypass_count = %u\n",

		   i915->uncore.user_forcewake.count);

		   uncore->user_forcewake.count);



	for_each_fw_domain(fw_domain, i915, tmp)

	for_each_fw_domain(fw_domain, uncore, tmp)

		seq_printf(m, "%s.wake_count = %u\n",

			   intel_uncore_forcewake_domain_to_str(fw_domain->id),

			   READ_ONCE(fw_domain->wake_count));
@@ -2059,12 +2059,12 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) 
		u32 rpup, rpupei;

		u32 rpdown, rpdownei;



		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);

		rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;

		rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;

		rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;

		rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;

		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);



		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",

			   rps_power_to_str(rps->power.mode));
@@ -4250,7 +4250,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) 
		return 0;



	file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915);

	intel_uncore_forcewake_user_get(i915);

	intel_uncore_forcewake_user_get(&i915->uncore);



	return 0;

}
@@ -4262,7 +4262,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) 
	if (INTEL_GEN(i915) < 6)

		return 0;



	intel_uncore_forcewake_user_put(i915);

	intel_uncore_forcewake_user_put(&i915->uncore);

	intel_runtime_pm_put(i915,

			     (intel_wakeref_t)(uintptr_t)file->private_data);

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