Commit f144e67b authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



UAPI Changes:
- Report an error early instead of SIGBUS later when mmap beyond BO size

Core Changes:
- This includes backmerge of drm-next and two merges of Maarten's
  topic/hdr-formats

Driver Changes:
- Add Comet Lake (Gen9) PCI IDs to Coffee Lake ID list (Anusha)
- Add missing ICL PCI ID (Jose)
- Fix legacy gamma mode for ICL (Ville)
- Assume eDP is present on port A when there is no VBT (Thomas)
- Corrections to eDP training patterns (Jose)
- Fix PSR2 selective update corruption after PSR1 setup (Jose)
- Fix CRC mismatch error for DP link layer compliance (Aditya)
- Fix CNL DPLL readout and clean up code (Ville)
- Turn off the CUS when turning off a HDR plane (Ville)
- Avoid a race with execlist tasklet during race (Chris)
- Add missing CSC readout and clean up code (Ville)
- Avoid unnecessary wakeref during debugfs/drop_caches/set (Chris, Caz)
- Hold references to ring/HW context/context explicitly when used (Chris)

- Assume next platforms inherit old platform (Rodrigo)
- Use HWS indices rather than addresses for breadcrumbs (Chris)
- Add REG_BIT/REG_GENMASK and REG_FIELD_PREP macros (Jani)
- Convert crept in C99 types to kernel fixed size types (Jani)
- Avoid passing full dev_priv in forcewake functions (Daniele)
- Reset GuC on GPU reset (Sujaritha)
- Rework MG and Combo PLLs to vfuncs (Lucas)
- Explicitly track ppGTT size (Chris, Bob)
- Coding style improvements and code modularization (Ville)
- Selftest and debugging improvements (Chris)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# Conflicts:
#	drivers/gpu/drm/i915/intel_hdmi.c
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325124925.GA12726@jlahtine-desk.ger.corp.intel.com
parents 0bec6219 1284ec98

drivers/gpu/drm/i915/Makefile

+11 −0
Original line number Diff line number Diff line
@@ -56,6 +56,15 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o 
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o

i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o



# Test the headers are compilable as standalone units

i915-$(CONFIG_DRM_I915_WERROR) += \

	test_i915_active_types_standalone.o \

	test_i915_gem_context_types_standalone.o \

	test_i915_timeline_types_standalone.o \

	test_intel_context_types_standalone.o \

	test_intel_engine_types_standalone.o \

	test_intel_workarounds_types_standalone.o



# GEM code

i915-y += \

	  i915_active.o \
@@ -77,6 +86,7 @@ i915-y += \ 
	  i915_gem_tiling.o \

	  i915_gem_userptr.o \

	  i915_gemfs.o \

	  i915_globals.o \

	  i915_query.o \

	  i915_request.o \

	  i915_scheduler.o \
@@ -84,6 +94,7 @@ i915-y += \ 
	  i915_trace_points.o \

	  i915_vma.o \

	  intel_breadcrumbs.o \

	  intel_context.o \

	  intel_engine_cs.o \

	  intel_hangcheck.o \

	  intel_lrc.o \

drivers/gpu/drm/i915/gvt/cmd_parser.c

+20 −24
Original line number Diff line number Diff line
@@ -391,12 +391,12 @@ struct cmd_info { 
#define F_POST_HANDLE	(1<<2)

	u32 flag;



#define R_RCS	(1 << RCS)

#define R_VCS1  (1 << VCS)

#define R_VCS2  (1 << VCS2)

#define R_RCS	BIT(RCS0)

#define R_VCS1  BIT(VCS0)

#define R_VCS2  BIT(VCS1)

#define R_VCS	(R_VCS1 | R_VCS2)

#define R_BCS	(1 << BCS)

#define R_VECS	(1 << VECS)

#define R_BCS	BIT(BCS0)

#define R_VECS	BIT(VECS0)

#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)

	/* rings that support this cmd: BLT/RCS/VCS/VECS */

	u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = { 
};



static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {

	[RCS] = {

	[RCS0] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -569,7 +569,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[VCS] = {

	[VCS0] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -580,7 +580,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[BCS] = {

	[BCS0] = {

		&decode_info_mi,

		NULL,

		&decode_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[VECS] = {

	[VECS0] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -602,7 +602,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 
		NULL,

	},



	[VCS2] = {

	[VCS1] = {

		&decode_info_mi,

		NULL,

		NULL,
@@ -631,8 +631,7 @@ static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, 
	struct cmd_entry *e;



	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {

		if ((opcode == e->info->opcode) &&

				(e->info->rings & (1 << ring_id)))

		if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))

			return e->info;

	}

	return NULL;
@@ -943,15 +942,12 @@ static int cmd_handler_lri(struct parser_exec_state *s) 
	struct intel_gvt *gvt = s->vgpu->gvt;



	for (i = 1; i < cmd_len; i += 2) {

		if (IS_BROADWELL(gvt->dev_priv) &&

				(s->ring_id != RCS)) {

			if (s->ring_id == BCS &&

					cmd_reg(s, i) ==

					i915_mmio_reg_offset(DERRMR))

		if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {

			if (s->ring_id == BCS0 &&

			    cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))

				ret |= 0;

			else

				ret |= (cmd_reg_inhibit(s, i)) ?

					-EBADRQC : 0;

				ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;

		}

		if (ret)

			break;
@@ -1047,27 +1043,27 @@ struct cmd_interrupt_event { 
};



static struct cmd_interrupt_event cmd_interrupt_events[] = {

	[RCS] = {

	[RCS0] = {

		.pipe_control_notify = RCS_PIPE_CONTROL,

		.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,

		.mi_user_interrupt = RCS_MI_USER_INTERRUPT,

	},

	[BCS] = {

	[BCS0] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = BCS_MI_FLUSH_DW,

		.mi_user_interrupt = BCS_MI_USER_INTERRUPT,

	},

	[VCS] = {

	[VCS0] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = VCS_MI_FLUSH_DW,

		.mi_user_interrupt = VCS_MI_USER_INTERRUPT,

	},

	[VCS2] = {

	[VCS1] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = VCS2_MI_FLUSH_DW,

		.mi_user_interrupt = VCS2_MI_USER_INTERRUPT,

	},

	[VECS] = {

	[VECS0] = {

		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,

		.mi_flush_dw = VECS_MI_FLUSH_DW,

		.mi_user_interrupt = VECS_MI_USER_INTERRUPT,

drivers/gpu/drm/i915/gvt/dmabuf.c

+1 −1
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_gem_object *obj;



	obj = i915_gem_object_alloc(dev_priv);

	obj = i915_gem_object_alloc();

	if (obj == NULL)

		return NULL;

drivers/gpu/drm/i915/gvt/execlist.c

+8 −9
Original line number Diff line number Diff line
@@ -47,17 +47,16 @@ 
		((a)->lrca == (b)->lrca))



static int context_switch_events[] = {

	[RCS] = RCS_AS_CONTEXT_SWITCH,

	[BCS] = BCS_AS_CONTEXT_SWITCH,

	[VCS] = VCS_AS_CONTEXT_SWITCH,

	[VCS2] = VCS2_AS_CONTEXT_SWITCH,

	[VECS] = VECS_AS_CONTEXT_SWITCH,

	[RCS0]  = RCS_AS_CONTEXT_SWITCH,

	[BCS0]  = BCS_AS_CONTEXT_SWITCH,

	[VCS0]  = VCS_AS_CONTEXT_SWITCH,

	[VCS1]  = VCS2_AS_CONTEXT_SWITCH,

	[VECS0] = VECS_AS_CONTEXT_SWITCH,

};



static int ring_id_to_context_switch_event(int ring_id)

static int ring_id_to_context_switch_event(unsigned int ring_id)

{

	if (WARN_ON(ring_id < RCS ||

		    ring_id >= ARRAY_SIZE(context_switch_events)))

	if (WARN_ON(ring_id >= ARRAY_SIZE(context_switch_events)))

		return -EINVAL;



	return context_switch_events[ring_id];
@@ -411,7 +410,7 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload) 
	gvt_dbg_el("complete workload %p status %d\n", workload,

			workload->status);



	if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id)))

	if (workload->status || (vgpu->resetting_eng & BIT(ring_id)))

		goto out;



	if (!list_empty(workload_q_head(vgpu, ring_id))) {

drivers/gpu/drm/i915/gvt/handlers.c

+13 −13
Original line number Diff line number Diff line
@@ -323,25 +323,25 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
	} else {

		if (data & GEN6_GRDOM_RENDER) {

			gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);

			engine_mask |= (1 << RCS);

			engine_mask |= BIT(RCS0);

		}

		if (data & GEN6_GRDOM_MEDIA) {

			gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);

			engine_mask |= (1 << VCS);

			engine_mask |= BIT(VCS0);

		}

		if (data & GEN6_GRDOM_BLT) {

			gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);

			engine_mask |= (1 << BCS);

			engine_mask |= BIT(BCS0);

		}

		if (data & GEN6_GRDOM_VECS) {

			gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);

			engine_mask |= (1 << VECS);

			engine_mask |= BIT(VECS0);

		}

		if (data & GEN8_GRDOM_MEDIA2) {

			gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);

			if (HAS_BSD2(vgpu->gvt->dev_priv))

				engine_mask |= (1 << VCS2);

			engine_mask |= BIT(VCS1);

		}

		engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;

	}



	/* vgpu_lock already hold by emulate mmio r/w */
@@ -1704,7 +1704,7 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
			return 0;



		ret = intel_vgpu_select_submission_ops(vgpu,

			       ENGINE_MASK(ring_id),

			       BIT(ring_id),

			       INTEL_VGPU_EXECLIST_SUBMISSION);

		if (ret)

			return ret;
@@ -1724,19 +1724,19 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 


	switch (offset) {

	case 0x4260:

		id = RCS;

		id = RCS0;

		break;

	case 0x4264:

		id = VCS;

		id = VCS0;

		break;

	case 0x4268:

		id = VCS2;

		id = VCS1;

		break;

	case 0x426c:

		id = BCS;

		id = BCS0;

		break;

	case 0x4270:

		id = VECS;

		id = VECS0;

		break;

	default:

		return -EINVAL;
@@ -1793,7 +1793,7 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 
	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \

	if (HAS_BSD2(dev_priv)) \

	if (HAS_ENGINE(dev_priv, VCS1)) \

		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \

} while (0)

CRA Git | Maintained and supported by SUSTech CRA and CCSE