Unverified Commit dd657eae authored by Maxime Ripard's avatar Maxime Ripard Committed by Mark Brown
Browse files

ASoC: sun4i-i2s: Fix the LRCK polarity



The LRCK polarity "normal" polarity in the I2S/TDM specs and in the
Allwinner datasheet are not the same. In the case where the i2s controller
is being used as the LRCK master, it's pretty clear when looked at under a
scope.

Let's fix this, and add a comment to clear up as much the confusion as
possible.

Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3")
Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T")
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://lore.kernel.org/r/e03fb6b2a916223070b9f18405b0ef117a452ff4.1566242458.git-series.maxime.ripard@bootlin.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 515fcfbc
Loading
Loading
Loading
Loading
+12 −6
Original line number Diff line number Diff line
@@ -570,23 +570,29 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
	u32 mode, val;
	u8 offset;

	/* DAI clock polarity */
	/*
	 * DAI clock polarity
	 *
	 * The setup for LRCK contradicts the datasheet, but under a
	 * scope it's clear that the LRCK polarity is reversed
	 * compared to the expected polarity on the bus.
	 */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_IF:
		/* Invert both clocks */
		val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
		      SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
		val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/* Invert bit clock */
		val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
		val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
		      SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* Invert frame clock */
		val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
		val = 0;
		break;
	case SND_SOC_DAIFMT_NB_NF:
		val = 0;
		val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
		break;
	default:
		return -EINVAL;