Unverified Commit 21faaea1 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Mark Brown
Browse files

ASoC: sun4i-i2s: Add support for A83T 



The I2S controller in the A83T is mostly compatible with the one found
in earlier SoCs such as the A20 and A31. While the documents publicly
available for the A83T do not cover this hardware, the officially
released BSP kernel does have register definitions for it. These were
matched against the A20 user manual. The only difference is the TX FIFO
and interrupt status registers have been swapped around, like what we
have seen with the SPDIF controller.

This patch adds support for this hardware.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4fbd8d19

Documentation/devicetree/bindings/sound/sun4i-i2s.txt

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required properties: 
- compatible: should be one of the following:

   - "allwinner,sun4i-a10-i2s"

   - "allwinner,sun6i-a31-i2s"

   - "allwinner,sun8i-a83t-i2s"

   - "allwinner,sun8i-h3-i2s"

- reg: physical base address of the controller and length of memory mapped

  region.
@@ -23,6 +24,7 @@ Required properties: 


Required properties for the following compatibles:

	- "allwinner,sun6i-a31-i2s"

	- "allwinner,sun8i-a83t-i2s"

	- "allwinner,sun8i-h3-i2s"

- resets: phandle to the reset line for this codec

sound/soc/sunxi/sun4i-i2s.c

+21 −0
Original line number Diff line number Diff line
@@ -897,6 +897,23 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { 
	.field_rxchansel	= REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),

};



static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {

	.has_reset		= true,

	.reg_offset_txdata	= SUN8I_I2S_FIFO_TX_REG,

	.sun4i_i2s_regmap	= &sun4i_i2s_regmap_config,

	.field_clkdiv_mclk_en	= REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),

	.field_fmt_wss		= REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),

	.field_fmt_sr		= REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),

	.field_fmt_bclk		= REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),

	.field_fmt_lrclk	= REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),

	.has_slave_select_bit	= true,

	.field_fmt_mode		= REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),

	.field_txchanmap	= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),

	.field_rxchanmap	= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),

	.field_txchansel	= REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),

	.field_rxchansel	= REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),

};



static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {

	.has_reset		= true,

	.reg_offset_txdata	= SUN8I_I2S_FIFO_TX_REG,
@@ -1120,6 +1137,10 @@ static const struct of_device_id sun4i_i2s_match[] = { 
		.compatible = "allwinner,sun6i-a31-i2s",

		.data = &sun6i_a31_i2s_quirks,

	},

	{

		.compatible = "allwinner,sun8i-a83t-i2s",

		.data = &sun8i_a83t_i2s_quirks,

	},

	{

		.compatible = "allwinner,sun8i-h3-i2s",

		.data = &sun8i_h3_i2s_quirks,

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