iommu/io-pgtable-arm: Rename IOMMU_QCOM_SYS_CACHE and improve doc (dd5ddd3c) · Commits · 戴 / test

The 'IOMMU_QCOM_SYS_CACHE' IOMMU protection flag is exposed to all users of the IOMMU API. Despite its name, the idea behind it isn't especially tied to Qualcomm implementations and could conceivably be used by other systems. Rename it to 'IOMMU_SYS_CACHE_ONLY' and update the comment to describe a bit better the idea behind it. Cc: Robin Murphy <robin.murphy@arm.com> Cc: "Isaac J. Manjarres" <isaacm@codeaurora.org> Signed-off-by:

Will Deacon <will@kernel.org>

drivers/iommu/io-pgtable-arm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -455,7 +455,7 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
		else if (prot & IOMMU_CACHE)
		pte \|= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
		<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
		else if (prot & IOMMU_QCOM_SYS_CACHE)
		else if (prot & IOMMU_SYS_CACHE_ONLY)
		pte \|= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
		<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
		}

include/linux/iommu.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -31,11 +31,11 @@
		*/
		#define IOMMU_PRIV (1 << 5)
		/*
		* Non-coherent masters on few Qualcomm SoCs can use this page protection flag
		* to set correct cacheability attributes to use an outer level of cache -
		* last level cache, aka system cache.
		* Non-coherent masters can use this page protection flag to set cacheable
		* memory attributes for only a transparent outer level of cache, also known as
		* the last-level or system cache.
		*/
		#define IOMMU_QCOM_SYS_CACHE (1 << 6)
		#define IOMMU_SYS_CACHE_ONLY (1 << 6)

		struct iommu_ops;
		struct iommu_group;

Admin message