Commit 205577ab authored by Robin Murphy's avatar Robin Murphy Committed by Will Deacon
Browse files

iommu/io-pgtable-arm: Rationalise MAIR handling 



Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.

Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 5fb190b0

drivers/iommu/arm-smmu-v3.c

+1 −1
Original line number Diff line number Diff line
@@ -2172,7 +2172,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, 
	cfg->cd.asid	= (u16)asid;

	cfg->cd.ttbr	= pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

	cfg->cd.tcr	= pgtbl_cfg->arm_lpae_s1_cfg.tcr;

	cfg->cd.mair	= pgtbl_cfg->arm_lpae_s1_cfg.mair[0];

	cfg->cd.mair	= pgtbl_cfg->arm_lpae_s1_cfg.mair;

	return 0;



out_free_asid:

drivers/iommu/arm-smmu.c

+2 −2
Original line number Diff line number Diff line
@@ -552,8 +552,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
			cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr;

			cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr;

		} else {

			cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];

			cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];

			cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair;

			cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32;

		}

	}

}

drivers/iommu/io-pgtable-arm.c

+1 −2
Original line number Diff line number Diff line
@@ -861,8 +861,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
	      (ARM_LPAE_MAIR_ATTR_INC_OWBRWA

	       << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));



	cfg->arm_lpae_s1_cfg.mair[0] = reg;

	cfg->arm_lpae_s1_cfg.mair[1] = 0;

	cfg->arm_lpae_s1_cfg.mair = reg;



	/* Looking good; allocate a pgd */

	data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),

drivers/iommu/ipmmu-vmsa.c

+1 −1
Original line number Diff line number Diff line
@@ -438,7 +438,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) 


	/* MAIR0 */

	ipmmu_ctx_write_root(domain, IMMAIR0,

			     domain->cfg.arm_lpae_s1_cfg.mair[0]);

			     domain->cfg.arm_lpae_s1_cfg.mair);



	/* IMBUSCR */

	if (domain->mmu->features->setup_imbuscr)

drivers/iommu/qcom_iommu.c

+2 −2
Original line number Diff line number Diff line
@@ -284,9 +284,9 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, 


		/* MAIRs (stage-1 only) */

		iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,

				pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);

				pgtbl_cfg.arm_lpae_s1_cfg.mair);

		iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,

				pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);

				pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);



		/* SCTLR */

		reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |

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