Commit dc6fcba7 authored Jan 05, 2020 by Guo Ren Committed by Paul Walmsley Jan 12, 2020

riscv: Fixup obvious bug for fp-regs reset



CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e806356 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

parent 13cf4cf0

arch/riscv/kernel/head.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -251,7 +251,7 @@ ENTRY(reset_regs)
		#ifdef CONFIG_FPU
		csrr t0, CSR_MISA
		andi t0, t0, (COMPAT_HWCAP_ISA_F \| COMPAT_HWCAP_ISA_D)
		bnez t0, .Lreset_regs_done
		beqz t0, .Lreset_regs_done

		li t1, SR_FS
		csrs CSR_STATUS, t1

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