clk: meson: axg: spread spectrum is on mpll2 (dc4e62d3) · Commits · 戴 / test

After testing, it appears that the SSEN bit controls the spread spectrum function on MPLL2, not MPLL0. Fixes: ("clk: meson-axg: add clock controller drivers") Signed-off-by:

Jerome Brunet <jbrunet@baylibre.com>

drivers/clk/meson/axg.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -469,11 +469,6 @@ static struct clk_regmap axg_mpll0_div = {
		.shift = 16,
		.width = 9,
		},
		.ssen = {
		.reg_off = HHI_MPLL_CNTL,
		.shift = 25,
		.width = 1,
		},
		.misc = {
		.reg_off = HHI_PLL_TOP_MISC,
		.shift = 0,
		@@ -568,6 +563,11 @@ static struct clk_regmap axg_mpll2_div = {
		.shift = 16,
		.width = 9,
		},
		.ssen = {
		.reg_off = HHI_MPLL_CNTL,
		.shift = 25,
		.width = 1,
		},
		.misc = {
		.reg_off = HHI_PLL_TOP_MISC,
		.shift = 2,

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