Commit dc0fa5eb authored by Shawn Guo's avatar Shawn Guo Committed by Rob Clark
Browse files

drm/msm/a4xx: add adreno a405 support 



It adds support for adreno a405 found on MSM8939.  The adreno_is_a430()
check in adreno_submit() needs an extension to cover a405.  The
downstream driver suggests it should cover the whole a4xx generation.
That's why it gets changed to adreno_is_a4xx(), while a420 is not
tested though.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Reviewed-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 24e6938e

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+17 −12
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) 
		}

	}



	/* No CCU for A405 */

	if (!adreno_is_a405(adreno_gpu)) {

		for (i = 0; i < 4; i++) {

			gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),

					0x00000922);
@@ -80,6 +82,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) 
			gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),

					0x00000001);

		}

	}



	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104);
@@ -137,7 +140,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	uint32_t *ptr, len;

	int i, ret;



	if (adreno_is_a420(adreno_gpu)) {

	if (adreno_is_a405(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);

	} else if (adreno_is_a420(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);

		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);

		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);

drivers/gpu/drm/msm/adreno/adreno_device.c

+11 −0
Original line number Diff line number Diff line
@@ -92,6 +92,17 @@ static const struct adreno_info gpulist[] = { 
		.gmem  = SZ_1M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(4, 0, 5, ANY_ID),

		.revn  = 405,

		.name  = "A405",

		.fw = {

			[ADRENO_FW_PM4] = "a420_pm4.fw",

			[ADRENO_FW_PFP] = "a420_pfp.fw",

		},

		.gmem  = SZ_256K,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a4xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(4, 2, 0, ANY_ID),

		.revn  = 420,

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -459,7 +459,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 
				break;

			/* fall-thru */

		case MSM_SUBMIT_CMD_BUF:

			OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?

			OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ?

				CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);

			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));

			OUT_RING(ring, submit->cmd[i].size);

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+5 −0
Original line number Diff line number Diff line
@@ -202,6 +202,11 @@ static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) 
	return (gpu->revn >= 400) && (gpu->revn < 500);

}



static inline int adreno_is_a405(struct adreno_gpu *gpu)

{

	return gpu->revn == 405;

}



static inline int adreno_is_a420(struct adreno_gpu *gpu)

{

	return gpu->revn == 420;

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