drm/msm/a6xx: update a6xx_hw_init for A640 and A650 (24e6938e) · Commits · 戴 / test

drivers/gpu/drm/msm/adreno/a6xx.xml.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -1047,6 +1047,8 @@ enum a6xx_tex_type {

		#define REG_A6XX_CP_MISC_CNTL 0x00000840

		#define REG_A6XX_CP_APRIV_CNTL 0x00000844

		#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1

		#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
		@@ -1764,6 +1766,8 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)

		#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010

		#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011

		#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f

		#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
		@@ -2418,6 +2422,16 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)

		#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604

		#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608

		#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609

		#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a

		#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b

		#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c

		#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610

		#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+47 −9

Original line number	Diff line number	Diff line
		@@ -414,7 +414,17 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		a6xx_set_hwcg(gpu, true);

		/* VBIF/GBIF start*/
		if (adreno_is_a640(adreno_gpu) \|\| adreno_is_a650(adreno_gpu)) {
		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
		} else {
		gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
		}

		if (adreno_is_a630(adreno_gpu))
		gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);

		@@ -429,6 +439,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
		gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);

		if (!adreno_is_a650(adreno_gpu)) {
		/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
		gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
		REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
		@@ -436,10 +447,14 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
		REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
		0x00100000 + adreno_gpu->gmem - 1);
		}

		gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
		gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);

		if (adreno_is_a640(adreno_gpu) \|\| adreno_is_a650(adreno_gpu))
		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
		else
		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);

		@@ -447,6 +462,11 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);

		/* Setting the primFifo thresholds default values */
		if (adreno_is_a650(adreno_gpu))
		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
		else if (adreno_is_a640(adreno_gpu))
		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
		else
		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));

		/* Set the AHB default slave response to "ERROR" */
		@@ -471,6 +491,19 @@ static int a6xx_hw_init(struct msm_gpu *gpu)

		gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);

		/* Set weights for bicubic filtering */
		if (adreno_is_a650(adreno_gpu)) {
		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
		0x3fe05ff4);
		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
		0x3fa0ebee);
		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
		0x3f5193ed);
		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
		0x3f0243f0);
		}

		/* Protect registers from the CP */
		gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);

		@@ -508,6 +541,11 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		A6XX_PROTECT_RDONLY(0x980, 0x4));
		gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));

		if (adreno_is_a650(adreno_gpu)) {
		gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
		(1 << 6) \| (1 << 5) \| (1 << 3) \| (1 << 2) \| (1 << 1));
		}

		/* Enable interrupts */
		gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);

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