Commit db29dc7d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2020-09-17' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Driver Changes:

- Reduce INTEL_DISPLAY_ENABLED to just removed outputs treating it as disconnected (Ville)
- Introducing new AUX, DVO, and TC ports and refactoring code around hot plug interrupts for those. (Ville)
- Centralize PLL_ENABLE register lookup (Anusha)
- Improvements around DP downstream facing ports (DFP). (Ville)
- Enable YCbCr 444->420 conversion for HDMI DFPs. Ville
- Remove the old global state on Display's atomic modeset (Ville)
- Nuke force_min_cdclk_changed (Ville)
- Extend a TGL W/A to all SKUs and to RKL (Swathi)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200918173013.GA748558@intel.com
parents 511d2ffd 8fea9253

drivers/acpi/acpi_lpss.c

+18 −4
Original line number Diff line number Diff line
@@ -67,7 +67,15 @@ ACPI_MODULE_NAME("acpi_lpss"); 
#define LPSS_CLK_DIVIDER		BIT(2)

#define LPSS_LTR			BIT(3)

#define LPSS_SAVE_CTX			BIT(4)

#define LPSS_NO_D3_DELAY		BIT(5)

/*

 * For some devices the DSDT AML code for another device turns off the device

 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)

 * as ctx register values.

 * Luckily these devices always use the same ctx register values, so we can

 * work around this by saving the ctx registers once on activation.

 */

#define LPSS_SAVE_CTX_ONCE		BIT(5)

#define LPSS_NO_D3_DELAY		BIT(6)



struct lpss_private_data;
@@ -254,9 +262,10 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { 
};



static const struct lpss_device_desc bsw_pwm_dev_desc = {

	.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,

	.flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,

	.prv_offset = 0x800,

	.setup = bsw_pwm_setup,

	.resume_from_noirq = true,

};



static const struct lpss_device_desc byt_uart_dev_desc = {
@@ -884,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) 
	 * we have to deassert reset line to be sure that ->probe() will

	 * recognize the device.

	 */

	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)

	if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))

		lpss_deassert_reset(pdata);



#ifdef CONFIG_PM

	if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)

		acpi_lpss_save_ctx(dev, pdata);

#endif



	return 0;

}
@@ -1030,7 +1044,7 @@ static int acpi_lpss_resume(struct device *dev) 


	acpi_lpss_d3_to_d0_delay(pdata);



	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)

	if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))

		acpi_lpss_restore_ctx(dev, pdata);



	return 0;

drivers/gpu/drm/drm_dp_helper.c

+344 −50
Original line number Diff line number Diff line
@@ -363,6 +363,66 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 
}

EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);



static bool is_edid_digital_input_dp(const struct edid *edid)

{

	return edid && edid->revision >= 4 &&

		edid->input & DRM_EDID_INPUT_DIGITAL &&

		(edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;

}



/**

 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 *

 * Caveat: Only works with DPCD 1.1+ port caps.

 *

 * Returns: whether the downstream facing port matches the type.

 */

bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			       const u8 port_cap[4], u8 type)

{

	return drm_dp_is_branch(dpcd) &&

		dpcd[DP_DPCD_REV] >= 0x11 &&

		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;

}

EXPORT_SYMBOL(drm_dp_downstream_is_type);



/**

 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 * @edid: EDID

 *

 * Returns: whether the downstream facing port is TMDS (HDMI/DVI).

 */

bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			       const u8 port_cap[4],

			       const struct edid *edid)

{

	if (dpcd[DP_DPCD_REV] < 0x11) {

		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {

		case DP_DWN_STRM_PORT_TYPE_TMDS:

			return true;

		default:

			return false;

		}

	}



	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		if (is_edid_digital_input_dp(edid))

			return false;

		fallthrough;

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_HDMI:

		return true;

	default:

		return false;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_is_tmds);



/**

 * drm_dp_send_real_edid_checksum() - send back real edid checksum value

 * @aux: DisplayPort AUX channel
@@ -545,79 +605,191 @@ int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 
	ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);

	if (ret < 0)

		return ret;

	if (ret != len)

		return -EIO;



	DRM_DEBUG_KMS("%s: DPCD DFP: %*ph\n",

		      aux->name, len, downstream_ports);



	return ret == len ? 0 : -EIO;

	return 0;

}

EXPORT_SYMBOL(drm_dp_read_downstream_info);



/**

 * drm_dp_downstream_max_clock() - extract branch device max

 *                                 pixel rate for legacy VGA

 *                                 converter or max TMDS clock

 *                                 rate for others

 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 *

 * See also:

 * drm_dp_read_downstream_info()

 * drm_dp_downstream_max_bpc()

 *

 * Returns: Max clock in kHz on success or 0 if max clock not defined

 * Returns: Downstream facing port max dot clock in kHz on success,

 * or 0 if max clock not defined

 */

int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

				   const u8 port_cap[4])

{

	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;

	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

		DP_DETAILED_CAP_INFO_AVAILABLE;

	if (!drm_dp_is_branch(dpcd))

		return 0;



	if (!detailed_cap_info)

	if (dpcd[DP_DPCD_REV] < 0x11)

		return 0;



	switch (type) {

	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_VGA:

		return port_cap[1] * 8 * 1000;

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_HDMI:

		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)

			return 0;

		return port_cap[1] * 8000;

	default:

		return 0;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);



/**

 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 * @edid: EDID

 *

 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,

 * or 0 if max TMDS clock not defined

 */

int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

				     const u8 port_cap[4],

				     const struct edid *edid)

{

	if (!drm_dp_is_branch(dpcd))

		return 0;



	if (dpcd[DP_DPCD_REV] < 0x11) {

		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {

		case DP_DWN_STRM_PORT_TYPE_TMDS:

			return 165000;

		default:

			return 0;

		}

	}



	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		if (is_edid_digital_input_dp(edid))

			return 0;

		/*

		 * It's left up to the driver to check the

		 * DP dual mode adapter's max TMDS clock.

		 *

		 * Unfortunatley it looks like branch devices

		 * may not fordward that the DP dual mode i2c

		 * access so we just usually get i2c nak :(

		 */

		fallthrough;

	case DP_DS_PORT_TYPE_HDMI:

		 /*

		  * We should perhaps assume 165 MHz when detailed cap

		  * info is not available. But looks like many typical

		  * branch devices fall into that category and so we'd

		  * probably end up with users complaining that they can't

		  * get high resolution modes with their favorite dongle.

		  *

		  * So let's limit to 300 MHz instead since DPCD 1.4

		  * HDMI 2.0 DFPs are required to have the detailed cap

		  * info. So it's more likely we're dealing with a HDMI 1.4

		  * compatible* device here.

		  */

		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)

			return 300000;

		return port_cap[1] * 2500;

	case DP_DS_PORT_TYPE_DVI:

		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)

			return 165000;

		/* FIXME what to do about DVI dual link? */

		return port_cap[1] * 2500;

	default:

		return 0;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_max_clock);

EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);



/**

 * drm_dp_downstream_max_bpc() - extract branch device max

 *                               bits per component

 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 * @edid: EDID

 *

 * See also:

 * drm_dp_read_downstream_info()

 * drm_dp_downstream_max_clock()

 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,

 * or 0 if max TMDS clock not defined

 */

int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

				     const u8 port_cap[4],

				     const struct edid *edid)

{

	if (!drm_dp_is_branch(dpcd))

		return 0;



	if (dpcd[DP_DPCD_REV] < 0x11) {

		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {

		case DP_DWN_STRM_PORT_TYPE_TMDS:

			return 25000;

		default:

			return 0;

		}

	}



	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		if (is_edid_digital_input_dp(edid))

			return 0;

		fallthrough;

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_HDMI:

		/*

		 * Unclear whether the protocol converter could

		 * utilize pixel replication. Assume it won't.

		 */

		return 25000;

	default:

		return 0;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);



/**

 * drm_dp_downstream_max_bpc() - extract downstream facing port max

 *                               bits per component

 * @dpcd: DisplayPort configuration data

 * @port_cap: downstream facing port capabilities

 * @edid: EDID

 *

 * Returns: Max bpc on success or 0 if max bpc not defined

 */

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			      const u8 port_cap[4])

			      const u8 port_cap[4],

			      const struct edid *edid)

{

	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;

	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

		DP_DETAILED_CAP_INFO_AVAILABLE;

	int bpc;

	if (!drm_dp_is_branch(dpcd))

		return 0;



	if (!detailed_cap_info)

	if (dpcd[DP_DPCD_REV] < 0x11) {

		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {

		case DP_DWN_STRM_PORT_TYPE_DP:

			return 0;

		default:

			return 8;

		}

	}



	switch (type) {

	case DP_DS_PORT_TYPE_VGA:

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_HDMI:

	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_DP:

		return 0;

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;

		if (is_edid_digital_input_dp(edid))

			return 0;

		fallthrough;

	case DP_DS_PORT_TYPE_HDMI:

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_VGA:

		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)

			return 8;



		switch (bpc) {

		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {

		case DP_DS_8BPC:

			return 8;

		case DP_DS_10BPC:
@@ -626,14 +798,130 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 
			return 12;

		case DP_DS_16BPC:

			return 16;

		default:

			return 8;

		}

		fallthrough;

		break;

	default:

		return 0;

		return 8;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_max_bpc);



/**

 * drm_dp_downstream_420_passthrough() - determine downstream facing port

 *                                       YCbCr 4:2:0 pass-through capability

 * @dpcd: DisplayPort configuration data

 * @port_cap: downstream facing port capabilities

 *

 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0

 */

bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

				       const u8 port_cap[4])

{

	if (!drm_dp_is_branch(dpcd))

		return false;



	if (dpcd[DP_DPCD_REV] < 0x13)

		return false;



	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_DP:

		return true;

	case DP_DS_PORT_TYPE_HDMI:

		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)

			return false;



		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;

	default:

		return false;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);



/**

 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port

 *                                             YCbCr 4:4:4->4:2:0 conversion capability

 * @dpcd: DisplayPort configuration data

 * @port_cap: downstream facing port capabilities

 *

 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0

 */

bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

					     const u8 port_cap[4])

{

	if (!drm_dp_is_branch(dpcd))

		return false;



	if (dpcd[DP_DPCD_REV] < 0x13)

		return false;



	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_HDMI:

		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)

			return false;



		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;

	default:

		return false;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);



/**

 * drm_dp_downstream_mode() - return a mode for downstream facing port

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 *

 * Provides a suitable mode for downstream facing ports without EDID.

 *

 * Returns: A new drm_display_mode on success or NULL on failure

 */

struct drm_display_mode *

drm_dp_downstream_mode(struct drm_device *dev,

		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],

		       const u8 port_cap[4])



{

	u8 vic;



	if (!drm_dp_is_branch(dpcd))

		return NULL;



	if (dpcd[DP_DPCD_REV] < 0x11)

		return NULL;



	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {

	case DP_DS_PORT_TYPE_NON_EDID:

		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {

		case DP_DS_NON_EDID_720x480i_60:

			vic = 6;

			break;

		case DP_DS_NON_EDID_720x480i_50:

			vic = 21;

			break;

		case DP_DS_NON_EDID_1920x1080i_60:

			vic = 5;

			break;

		case DP_DS_NON_EDID_1920x1080i_50:

			vic = 20;

			break;

		case DP_DS_NON_EDID_1280x720_60:

			vic = 4;

			break;

		case DP_DS_NON_EDID_1280x720_50:

			vic = 19;

			break;

		default:

			return NULL;

		}

		return drm_display_mode_from_cea_vic(dev, vic);

	default:

		return NULL;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_mode);



/**

 * drm_dp_downstream_id() - identify branch device

 * @aux: DisplayPort AUX channel
@@ -652,12 +940,15 @@ EXPORT_SYMBOL(drm_dp_downstream_id); 
 * @m: pointer for debugfs file

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 * @edid: EDID

 * @aux: DisplayPort AUX channel

 *

 */

void drm_dp_downstream_debug(struct seq_file *m,

			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			     const u8 port_cap[4], struct drm_dp_aux *aux)

			     const u8 port_cap[4],

			     const struct edid *edid,

			     struct drm_dp_aux *aux)

{

	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

				 DP_DETAILED_CAP_INFO_AVAILABLE;
@@ -715,16 +1006,19 @@ void drm_dp_downstream_debug(struct seq_file *m, 
		seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);



	if (detailed_cap_info) {

		clk = drm_dp_downstream_max_clock(dpcd, port_cap);



		if (clk > 0) {

			if (type == DP_DS_PORT_TYPE_VGA)

		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);

		if (clk > 0)

			seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);

			else



		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);

		if (clk > 0)

			seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);

		}



		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);

		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);

		if (clk > 0)

			seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);



		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);



		if (bpc > 0)

			seq_printf(m, "\t\tMax bpc: %d\n", bpc);

drivers/gpu/drm/drm_dp_mst_topology.c

+150 −0
Original line number Diff line number Diff line
@@ -20,11 +20,13 @@ 
 * OF THIS SOFTWARE.

 */



#include <linux/bitfield.h>

#include <linux/delay.h>

#include <linux/errno.h>

#include <linux/i2c.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/random.h>

#include <linux/sched.h>

#include <linux/seq_file.h>

#include <linux/iopoll.h>
@@ -423,6 +425,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, 
		memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes);

		idx += req->u.i2c_write.num_bytes;

		break;

	case DP_QUERY_STREAM_ENC_STATUS: {

		const struct drm_dp_query_stream_enc_status *msg;



		msg = &req->u.enc_status;

		buf[idx] = msg->stream_id;

		idx++;

		memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id));

		idx += sizeof(msg->client_id);

		buf[idx] = 0;

		buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);

		buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;

		buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);

		buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;

		idx++;

		}

		break;

	}

	raw->cur_len = idx;

}
@@ -551,6 +569,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, 
				return -ENOMEM;

		}

		break;

	case DP_QUERY_STREAM_ENC_STATUS:

		req->u.enc_status.stream_id = buf[idx++];

		for (i = 0; i < sizeof(req->u.enc_status.client_id); i++)

			req->u.enc_status.client_id[i] = buf[idx++];



		req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),

							   buf[idx]);

		req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2),

								 buf[idx]);

		req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),

							      buf[idx]);

		req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5),

								    buf[idx]);

		break;

	}



	return 0;
@@ -629,6 +661,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req 
		  req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes,

		  req->u.i2c_write.bytes);

		break;

	case DP_QUERY_STREAM_ENC_STATUS:

		P("stream_id=%u client_id=%*ph stream_event=%x "

		  "valid_event=%d stream_behavior=%x valid_behavior=%d",

		  req->u.enc_status.stream_id,

		  (int)ARRAY_SIZE(req->u.enc_status.client_id),

		  req->u.enc_status.client_id, req->u.enc_status.stream_event,

		  req->u.enc_status.valid_stream_event,

		  req->u.enc_status.stream_behavior,

		  req->u.enc_status.valid_stream_behavior);

		break;

	default:

		P("???\n");

		break;
@@ -936,6 +978,42 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms 
	return true;

}



static bool

drm_dp_sideband_parse_query_stream_enc_status(

				struct drm_dp_sideband_msg_rx *raw,

				struct drm_dp_sideband_msg_reply_body *repmsg)

{

	struct drm_dp_query_stream_enc_status_ack_reply *reply;



	reply = &repmsg->u.enc_status;



	reply->stream_id = raw->msg[3];



	reply->reply_signed = raw->msg[2] & BIT(0);



	/*

	 * NOTE: It's my impression from reading the spec that the below parsing

	 * is correct. However I noticed while testing with an HDCP 1.4 display

	 * through an HDCP 2.2 hub that only bit 3 was set. In that case, I

	 * would expect both bits to be set. So keep the parsing following the

	 * spec, but beware reality might not match the spec (at least for some

	 * configurations).

	 */

	reply->hdcp_1x_device_present = raw->msg[2] & BIT(4);

	reply->hdcp_2x_device_present = raw->msg[2] & BIT(3);



	reply->query_capable_device_present = raw->msg[2] & BIT(5);

	reply->legacy_device_present = raw->msg[2] & BIT(6);

	reply->unauthorizable_device_present = raw->msg[2] & BIT(7);



	reply->auth_completed = !!(raw->msg[1] & BIT(3));

	reply->encryption_enabled = !!(raw->msg[1] & BIT(4));

	reply->repeater_present = !!(raw->msg[1] & BIT(5));

	reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;



	return true;

}



static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,

					struct drm_dp_sideband_msg_reply_body *msg)

{
@@ -970,6 +1048,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, 
		return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg);

	case DP_CLEAR_PAYLOAD_ID_TABLE:

		return true; /* since there's nothing to parse */

	case DP_QUERY_STREAM_ENC_STATUS:

		return drm_dp_sideband_parse_query_stream_enc_status(raw, msg);

	default:

		DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,

			  drm_dp_mst_req_type_str(msg->req_type));
@@ -1121,6 +1201,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, 
	msg->path_msg = true;

}



static int

build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id,

			      u8 *q_id)

{

	struct drm_dp_sideband_msg_req_body req;



	req.req_type = DP_QUERY_STREAM_ENC_STATUS;

	req.u.enc_status.stream_id = stream_id;

	memcpy(req.u.enc_status.client_id, q_id,

	       sizeof(req.u.enc_status.client_id));

	req.u.enc_status.stream_event = 0;

	req.u.enc_status.valid_stream_event = false;

	req.u.enc_status.stream_behavior = 0;

	req.u.enc_status.valid_stream_behavior = false;



	drm_dp_encode_sideband_req(&req, msg);

	return 0;

}



static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr,

					struct drm_dp_vcpi *vcpi)

{
@@ -3153,6 +3252,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, 
}

EXPORT_SYMBOL(drm_dp_send_power_updown_phy);



int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

		struct drm_dp_mst_port *port,

		struct drm_dp_query_stream_enc_status_ack_reply *status)

{

	struct drm_dp_sideband_msg_tx *txmsg;

	u8 nonce[7];

	int len, ret;



	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);

	if (!txmsg)

		return -ENOMEM;



	port = drm_dp_mst_topology_get_port_validated(mgr, port);

	if (!port) {

		ret = -EINVAL;

		goto out_get_port;

	}



	get_random_bytes(nonce, sizeof(nonce));



	/*

	 * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message

	 *  transaction at the MST Branch device directly connected to the

	 *  Source"

	 */

	txmsg->dst = mgr->mst_primary;



	len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce);



	drm_dp_queue_down_tx(mgr, txmsg);



	ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg);

	if (ret < 0) {

		goto out;

	} else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) {

		drm_dbg_kms(mgr->dev, "query encryption status nak received\n");

		ret = -ENXIO;

		goto out;

	}



	ret = 0;

	memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status));



out:

	drm_dp_mst_topology_put_port(port);

out_get_port:

	kfree(txmsg);

	return ret;

}

EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status);



static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr,

				       int id,

				       struct drm_dp_payload *payload)

drivers/gpu/drm/drm_edid.c

+28 −0
Original line number Diff line number Diff line
@@ -3738,6 +3738,34 @@ drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 
	bitmap_set(hdmi->y420_cmdb_modes, vic, 1);

}



/**

 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC

 * @dev: DRM device

 * @vic: CEA VIC of the mode

 *

 * Creates a new mode matching the specified CEA VIC.

 *

 * Returns: A new drm_display_mode on success or NULL on failure

 */

struct drm_display_mode *

drm_display_mode_from_cea_vic(struct drm_device *dev,

			      u8 video_code)

{

	const struct drm_display_mode *cea_mode;

	struct drm_display_mode *newmode;



	cea_mode = cea_mode_for_vic(video_code);

	if (!cea_mode)

		return NULL;



	newmode = drm_mode_duplicate(dev, cea_mode);

	if (!newmode)

		return NULL;



	return newmode;

}

EXPORT_SYMBOL(drm_display_mode_from_cea_vic);



static int

do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)

{

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ i915-y += \ 
	display/intel_ddi.o \

	display/intel_dp.o \

	display/intel_dp_aux_backlight.o \

	display/intel_dp_hdcp.o \

	display/intel_dp_link_training.o \

	display/intel_dp_mst.o \

	display/intel_dsi.o \

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