Merge tag 'cdns-mhdp-5.10' of... (511d2ffd) · Commits · 戴 / test

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml

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		# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: Cadence MHDP8546 bridge

		maintainers:
		- Swapnil Jakhade <sjakhade@cadence.com>
		- Yuti Amonkar <yamonkar@cadence.com>

		properties:
		compatible:
		enum:
		- cdns,mhdp8546
		- ti,j721e-mhdp8546

		reg:
		minItems: 1
		maxItems: 2
		items:
		- description:
		Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
		The AUX and PMA registers are not part of this range, they are instead
		included in the associated PHY.
		- description:
		Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.

		reg-names:
		minItems: 1
		maxItems: 2
		items:
		- const: mhdptx
		- const: j721e-intg

		clocks:
		maxItems: 1
		description:
		DP bridge clock, used by the IP to know how to translate a number of
		clock cycles into a time (which is used to comply with DP standard timings
		and delays).

		phys:
		maxItems: 1
		description:
		phandle to the DisplayPort PHY.

		phy-names:
		items:
		- const: dpphy

		power-domains:
		maxItems: 1

		interrupts:
		maxItems: 1

		ports:
		type: object
		description:
		Ports as described in Documentation/devicetree/bindings/graph.txt.

		properties:
		'#address-cells':
		const: 1

		'#size-cells':
		const: 0

		port@0:
		type: object
		description:
		First input port representing the DP bridge input.

		port@1:
		type: object
		description:
		Second input port representing the DP bridge input.

		port@2:
		type: object
		description:
		Third input port representing the DP bridge input.

		port@3:
		type: object
		description:
		Fourth input port representing the DP bridge input.

		port@4:
		type: object
		description:
		Output port representing the DP bridge output.

		required:
		- port@0
		- port@4
		- '#address-cells'
		- '#size-cells'

		allOf:
		- if:
		properties:
		compatible:
		contains:
		const: ti,j721e-mhdp8546
		then:
		properties:
		reg:
		minItems: 2
		reg-names:
		minItems: 2
		else:
		properties:
		reg:
		maxItems: 1
		reg-names:
		maxItems: 1

		required:
		- compatible
		- clocks
		- reg
		- reg-names
		- phys
		- phy-names
		- interrupts
		- ports

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		bus {
		#address-cells = <2>;
		#size-cells = <2>;

		mhdp: dp-bridge@f0fb000000 {
		compatible = "cdns,mhdp8546";
		reg = <0xf0 0xfb000000 0x0 0x1000000>;
		reg-names = "mhdptx";
		clocks = <&mhdp_clock>;
		phys = <&dp_phy>;
		phy-names = "dpphy";
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dp_bridge_input: endpoint {
		remote-endpoint = <&xxx_dpi_output>;
		};
		};

		port@4 {
		reg = <4>;
		dp_bridge_output: endpoint {
		remote-endpoint = <&xxx_dp_connector_input>;
		};
		};
		};
		};
		};
		...

drivers/gpu/drm/bridge/Kconfig

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		@@ -241,6 +241,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"

		source "drivers/gpu/drm/bridge/adv7511/Kconfig"

		source "drivers/gpu/drm/bridge/cadence/Kconfig"

		source "drivers/gpu/drm/bridge/synopsys/Kconfig"

		endmenu

drivers/gpu/drm/bridge/Makefile

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		@@ -25,4 +25,5 @@ obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
		obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o

		obj-y += analogix/
		obj-y += cadence/
		obj-y += synopsys/

drivers/gpu/drm/bridge/cadence/Kconfig

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		# SPDX-License-Identifier: GPL-2.0-only
		config DRM_CDNS_MHDP8546
		tristate "Cadence DPI/DP bridge"
		select DRM_KMS_HELPER
		select DRM_PANEL_BRIDGE
		depends on OF
		help
		Support Cadence DPI to DP bridge. This is an internal
		bridge and is meant to be directly embedded in a SoC.
		It takes a DPI stream as input and outputs it encoded
		in DP format.

		if DRM_CDNS_MHDP8546

		config DRM_CDNS_MHDP8546_J721E
		depends on ARCH_K3_J721E_SOC \|\| COMPILE_TEST
		bool "J721E Cadence DPI/DP wrapper support"
		default y
		help
		Support J721E Cadence DPI/DP wrapper. This is a wrapper
		which adds support for J721E related platform ops. It
		initializes the J721E Display Port and sets up the
		clock and data muxes.
		endif

drivers/gpu/drm/bridge/cadence/Makefile

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		# SPDX-License-Identifier: GPL-2.0-only
		obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
		cdns-mhdp8546-y := cdns-mhdp8546-core.o
		cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

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