Commit da99f935 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "Fixes and HW enablement patches:

   - Tooling fixes, most of which are tooling header synchronization
     with v5.6 changes

   - Fix kprobes fallout on ARM

   - Add Intel Elkhart Lake support and extend Tremont support, these
     are relatively simple and should only affect those models

   - Fix the AMD family 17h generic event table"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (30 commits)
  perf llvm: Fix script used to obtain kernel make directives to work with new kbuild
  tools headers kvm: Sync linux/kvm.h with the kernel sources
  tools headers kvm: Sync kvm headers with the kernel sources
  tools arch x86: Sync asm/cpufeatures.h with the kernel sources
  tools headers x86: Sync disabled-features.h
  tools include UAPI: Sync sound/asound.h copy
  tools headers UAPI: Sync asm-generic/mman-common.h with the kernel
  perf tools: Add arm64 version of get_cpuid()
  tools headers UAPI: Sync drm/i915_drm.h with the kernel sources
  tools headers uapi: Sync linux/fscrypt.h with the kernel sources
  tools headers UAPI: Sync sched.h with the kernel
  perf trace: Resolve prctl's 'option' arg strings to numbers
  perf beauty prctl: Export the 'options' strarray
  tools headers UAPI: Sync prctl.h with the kernel sources
  tools headers UAPI: Sync copy of arm64's asm/unistd.h with the kernel sources
  perf maps: Move kmap::kmaps setup to maps__insert()
  perf maps: Fix map__clone() for struct kmap
  perf maps: Mark ksymbol DSOs with kernel type
  perf maps: Mark module DSOs with kernel type
  tools include UAPI: Sync x86's syscalls_64.tbl, generic unistd.h and fcntl.h to pick up openat2 and pidfd_getfd
  ...
parents 829e6944 dfb9b69e

arch/arm/kernel/ftrace.c

+2 −5
Original line number Diff line number Diff line
@@ -78,13 +78,10 @@ static int ftrace_modify_code(unsigned long pc, unsigned long old, 
{

	unsigned long replaced;



	if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {

	if (IS_ENABLED(CONFIG_THUMB2_KERNEL))

		old = __opcode_to_mem_thumb32(old);

		new = __opcode_to_mem_thumb32(new);

	} else {

	else

		old = __opcode_to_mem_arm(old);

		new = __opcode_to_mem_arm(new);

	}



	if (validate) {

		if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE))

arch/arm/kernel/patch.c

+9 −10
Original line number Diff line number Diff line
@@ -16,10 +16,10 @@ struct patch { 
	unsigned int insn;

};



#ifdef CONFIG_MMU

static DEFINE_RAW_SPINLOCK(patch_lock);



static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)

	__acquires(&patch_lock)

{

	unsigned int uintaddr = (uintptr_t) addr;

	bool module = !core_kernel_text(uintaddr);
@@ -34,8 +34,6 @@ static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags) 


	if (flags)

		raw_spin_lock_irqsave(&patch_lock, *flags);

	else

		__acquire(&patch_lock);



	set_fixmap(fixmap, page_to_phys(page));
@@ -43,15 +41,19 @@ static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags) 
}



static void __kprobes patch_unmap(int fixmap, unsigned long *flags)

	__releases(&patch_lock)

{

	clear_fixmap(fixmap);



	if (flags)

		raw_spin_unlock_irqrestore(&patch_lock, *flags);

	else

		__release(&patch_lock);

}

#else

static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)

{

	return addr;

}

static void __kprobes patch_unmap(int fixmap, unsigned long *flags) { }

#endif



void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap)

{
@@ -64,8 +66,6 @@ void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap) 


	if (remap)

		waddr = patch_map(addr, FIX_TEXT_POKE0, &flags);

	else

		__acquire(&patch_lock);



	if (thumb2 && __opcode_is_thumb16(insn)) {

		*(u16 *)waddr = __opcode_to_mem_thumb16(insn);
@@ -102,8 +102,7 @@ void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap) 
	if (waddr != addr) {

		flush_kernel_vmap_range(waddr, twopage ? size / 2 : size);

		patch_unmap(FIX_TEXT_POKE0, &flags);

	} else

		__release(&patch_lock);

	}



	flush_icache_range((uintptr_t)(addr),

			   (uintptr_t)(addr) + size);

arch/x86/events/amd/core.c

+1 −0
Original line number Diff line number Diff line
@@ -250,6 +250,7 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = 
	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x0287,

arch/x86/events/intel/core.c

+1 −0
Original line number Diff line number Diff line
@@ -4765,6 +4765,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_ATOM_TREMONT_D:

	case INTEL_FAM6_ATOM_TREMONT:

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

arch/x86/events/intel/cstate.c

+13 −9
Original line number Diff line number Diff line
@@ -40,17 +40,18 @@ 
 * Model specific counters:

 *	MSR_CORE_C1_RES: CORE C1 Residency Counter

 *			 perf code: 0x00

 *			 Available model: SLM,AMT,GLM,CNL

 *			 Available model: SLM,AMT,GLM,CNL,TNT

 *			 Scope: Core (each processor core has a MSR)

 *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,

 *						CNL,KBL,CML

 *						CNL,KBL,CML,TNT

 *			       Scope: Core

 *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,

 *						TNT

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03
@@ -60,17 +61,18 @@ 
 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,

 *						KBL,CML,ICL,TGL

 *						KBL,CML,ICL,TGL,TNT

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

 *						GLM,CNL,KBL,CML,ICL,TGL

 *						GLM,CNL,KBL,CML,ICL,TGL,TNT

 *			       Scope: Package (physical package)

 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,

 *						TNT

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03
@@ -87,7 +89,8 @@ 
 *			       Scope: Package (physical package)

 *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.

 *			       perf code: 0x06

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,

 *						TNT

 *			       Scope: Package (physical package)

 *

 */
@@ -640,8 +643,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 


	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT,   glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT_D, glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT, glm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE,   icl_cstates),

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