Commit d9df942c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.1-tag1' of... 

Merge tag 'clk-renesas-for-v5.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add missing CANFD clocks on RZ/G2M and RZ/G2E,
  - Correct the DU (display unit) parent clock on RZ/G2E.

* tag 'clk-renesas-for-v5.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a774c0: Correct parent clock of DU
  clk: renesas: r8a774a1: Add missing CANFD clock
  clk: renesas: r8a774c0: Add missing CANFD clock
parents bfeffd15 d9286d97

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A774A1_CLK_CPEX,  CLK_EXTAL,      2, 1),



	DEF_DIV6P1("canfd",     R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("csi0",      R8A774A1_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),

	DEF_DIV6P1("mso",       R8A774A1_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

	DEF_DIV6P1("hdmi",      R8A774A1_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
@@ -191,6 +192,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("gpio2",		 910,	R8A774A1_CLK_S3D4),

	DEF_MOD("gpio1",		 911,	R8A774A1_CLK_S3D4),

	DEF_MOD("gpio0",		 912,	R8A774A1_CLK_S3D4),

	DEF_MOD("can-fd",		 914,	R8A774A1_CLK_S3D2),

	DEF_MOD("can-if1",		 915,	R8A774A1_CLK_S3D4),

	DEF_MOD("can-if0",		 916,	R8A774A1_CLK_S3D4),

	DEF_MOD("i2c6",			 918,	R8A774A1_CLK_S0D6),

drivers/clk/renesas/r8a774c0-cpg-mssr.c

+6 −2
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ enum clk_ids { 
	CLK_PLL1,

	CLK_PLL3,

	CLK_PLL0D4,

	CLK_PLL0D6,

	CLK_PLL0D8,

	CLK_PLL0D20,

	CLK_PLL0D24,
@@ -61,6 +62,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { 


	DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,	   1, 100),

	DEF_FIXED(".pll0d4",   CLK_PLL0D4,         CLK_PLL0,       4, 1),

	DEF_FIXED(".pll0d6",   CLK_PLL0D6,         CLK_PLL0,       6, 1),

	DEF_FIXED(".pll0d8",   CLK_PLL0D8,         CLK_PLL0,       8, 1),

	DEF_FIXED(".pll0d20",  CLK_PLL0D20,        CLK_PLL0,      20, 1),

	DEF_FIXED(".pll0d24",  CLK_PLL0D24,        CLK_PLL0,      24, 1),
@@ -112,6 +114,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { 
	DEF_GEN3_PE("s3d2c",   R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),

	DEF_GEN3_PE("s3d4c",   R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),



	DEF_DIV6P1("canfd",    R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244),

	DEF_DIV6P1("csi0",     R8A774C0_CLK_CSI0,  CLK_PLL1D2, 0x00c),

	DEF_DIV6P1("mso",      R8A774C0_CLK_MSO,   CLK_PLL1D2, 0x014),
@@ -172,8 +175,8 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 
	DEF_MOD("ehci0",		 703,	R8A774C0_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A774C0_CLK_S3D4),

	DEF_MOD("csi40",		 716,	R8A774C0_CLK_CSI0),

	DEF_MOD("du1",			 723,	R8A774C0_CLK_S2D1),

	DEF_MOD("du0",			 724,	R8A774C0_CLK_S2D1),

	DEF_MOD("du1",			 723,	R8A774C0_CLK_S1D1),

	DEF_MOD("du0",			 724,	R8A774C0_CLK_S1D1),

	DEF_MOD("lvds",			 727,	R8A774C0_CLK_S2D1),



	DEF_MOD("vin5",			 806,	R8A774C0_CLK_S1D2),
@@ -187,6 +190,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 
	DEF_MOD("gpio2",		 910,	R8A774C0_CLK_S3D4),

	DEF_MOD("gpio1",		 911,	R8A774C0_CLK_S3D4),

	DEF_MOD("gpio0",		 912,	R8A774C0_CLK_S3D4),

	DEF_MOD("can-fd",		 914,	R8A774C0_CLK_S3D2),

	DEF_MOD("can-if1",		 915,	R8A774C0_CLK_S3D4),

	DEF_MOD("can-if0",		 916,	R8A774C0_CLK_S3D4),

	DEF_MOD("i2c6",			 918,	R8A774C0_CLK_S3D2),

include/dt-bindings/clock/r8a774a1-cpg-mssr.h

+1 −0
Original line number Diff line number Diff line
@@ -54,5 +54,6 @@ 
#define R8A774A1_CLK_CPEX		43

#define R8A774A1_CLK_R			44

#define R8A774A1_CLK_OSC		45

#define R8A774A1_CLK_CANFD		46



#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

include/dt-bindings/clock/r8a774c0-cpg-mssr.h

+1 −0
Original line number Diff line number Diff line
@@ -56,5 +56,6 @@ 
#define R8A774C0_CLK_CSI0		45

#define R8A774C0_CLK_CP			46

#define R8A774C0_CLK_CPEX		47

#define R8A774C0_CLK_CANFD		48



#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */

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