Commit d9286d97 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a774c0: Correct parent clock of DU 



According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.

Fixes: 906e0a4a ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 9d034e15

drivers/clk/renesas/r8a774c0-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 
	DEF_MOD("ehci0",		 703,	R8A774C0_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A774C0_CLK_S3D4),

	DEF_MOD("csi40",		 716,	R8A774C0_CLK_CSI0),

	DEF_MOD("du1",			 723,	R8A774C0_CLK_S2D1),

	DEF_MOD("du0",			 724,	R8A774C0_CLK_S2D1),

	DEF_MOD("du1",			 723,	R8A774C0_CLK_S1D1),

	DEF_MOD("du0",			 724,	R8A774C0_CLK_S1D1),

	DEF_MOD("lvds",			 727,	R8A774C0_CLK_S2D1),



	DEF_MOD("vin5",			 806,	R8A774C0_CLK_S1D2),

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