Commit 9d034e15 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a774a1: Add missing CANFD clock 



This patch adds the missing CANFD clock to the r8a774a1 specific
clock driver.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarChris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 2a6efbc6

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A774A1_CLK_CPEX,  CLK_EXTAL,      2, 1),



	DEF_DIV6P1("canfd",     R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("csi0",      R8A774A1_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),

	DEF_DIV6P1("mso",       R8A774A1_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

	DEF_DIV6P1("hdmi",      R8A774A1_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
@@ -191,6 +192,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("gpio2",		 910,	R8A774A1_CLK_S3D4),

	DEF_MOD("gpio1",		 911,	R8A774A1_CLK_S3D4),

	DEF_MOD("gpio0",		 912,	R8A774A1_CLK_S3D4),

	DEF_MOD("can-fd",		 914,	R8A774A1_CLK_S3D2),

	DEF_MOD("can-if1",		 915,	R8A774A1_CLK_S3D4),

	DEF_MOD("can-if0",		 916,	R8A774A1_CLK_S3D4),

	DEF_MOD("i2c6",			 918,	R8A774A1_CLK_S0D6),

include/dt-bindings/clock/r8a774a1-cpg-mssr.h

+1 −0
Original line number Diff line number Diff line
@@ -54,5 +54,6 @@ 
#define R8A774A1_CLK_CPEX		43

#define R8A774A1_CLK_R			44

#define R8A774A1_CLK_OSC		45

#define R8A774A1_CLK_CANFD		46



#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

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