Commit d9cb5bfc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile 

Pull arch/tile updates from Chris Metcalf:
 "Another grab-bag of miscellaneous changes"

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  tile: use __ro_after_init instead of tile-specific __write_once
  tile: migrate exception table users off module.h and onto extable.h
  tile: remove #pragma unroll from finv_buffer_remote()
  tile-module: Rename jump labels in module_alloc()
  tile-module: Use kmalloc_array() in module_alloc()
  tile/pci_gx: fix spelling mistake: "delievered" -> "delivered"
parents 0f484e42 14e73e78

arch/tile/include/asm/cache.h

+2 −5
Original line number Diff line number Diff line
@@ -50,18 +50,15 @@ 


/*

 * Originally we used small TLB pages for kernel data and grouped some

 * things together as "write once", enforcing the property at the end

 * things together as ro-after-init, enforcing the property at the end

 * of initialization by making those pages read-only and non-coherent.

 * This allowed better cache utilization since cache inclusion did not

 * need to be maintained.  However, to do this requires an extra TLB

 * entry, which on balance is more of a performance hit than the

 * non-coherence is a performance gain, so we now just make "read

 * mostly" and "write once" be synonyms.  We keep the attribute

 * mostly" and "ro-after-init" be synonyms.  We keep the attribute

 * separate in case we change our minds at a future date.

 */

#define __write_once __read_mostly



/* __ro_after_init is the generic name for the tile arch __write_once. */

#define __ro_after_init __read_mostly



#endif /* _ASM_TILE_CACHE_H */

arch/tile/include/asm/sections.h

+0 −3
Original line number Diff line number Diff line
@@ -19,9 +19,6 @@ 


#include <asm-generic/sections.h>



/* Write-once data is writable only till the end of initialization. */

extern char __w1data_begin[], __w1data_end[];



extern char vdso_start[], vdso_end[];

#ifdef CONFIG_COMPAT

extern char vdso32_start[], vdso32_end[];

arch/tile/kernel/module.c

+5 −6
Original line number Diff line number Diff line
@@ -43,29 +43,28 @@ void *module_alloc(unsigned long size) 
	int npages;



	npages = (size + PAGE_SIZE - 1) / PAGE_SIZE;

	pages = kmalloc(npages * sizeof(struct page *), GFP_KERNEL);

	pages = kmalloc_array(npages, sizeof(*pages), GFP_KERNEL);

	if (pages == NULL)

		return NULL;

	for (; i < npages; ++i) {

		pages[i] = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);

		if (!pages[i])

			goto error;

			goto free_pages;

	}



	area = __get_vm_area(size, VM_ALLOC, MEM_MODULE_START, MEM_MODULE_END);

	if (!area)

		goto error;

		goto free_pages;

	area->nr_pages = npages;

	area->pages = pages;



	if (map_vm_area(area, prot_rwx, pages)) {

		vunmap(area->addr);

		goto error;

		goto free_pages;

	}



	return area->addr;



error:

 free_pages:

	while (--i >= 0)

		__free_page(pages[i]);

	kfree(pages);

arch/tile/kernel/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static int pci_probe = 1; 
 * This flag tells if the platform is TILEmpower that needs

 * special configuration for the PLX switch chip.

 */

int __write_once tile_plx_gen1;

int __ro_after_init tile_plx_gen1;



static struct pci_controller controllers[TILE_NUM_PCIE];

static int num_controllers;

arch/tile/kernel/pci_gx.c

+1 −1
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ static int tile_irq_cpu(int irq) 


	count = cpumask_weight(&intr_cpus_map);

	if (unlikely(count == 0)) {

		pr_warn("intr_cpus_map empty, interrupts will be delievered to dataplane tiles\n");

		pr_warn("intr_cpus_map empty, interrupts will be delivered to dataplane tiles\n");

		return irq % (smp_height * smp_width);

	}

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