Commit 14e73e78 authored by Chris Metcalf's avatar Chris Metcalf
Browse files

tile: use __ro_after_init instead of tile-specific __write_once 



The semantics of the old tile __write_once are the same as the
newer generic __ro_after_init, so rename them all and get rid
of the tile-specific version.

This does not enable actual support for __ro_after_init,
which had been dropped from the tile architecture before the
initial upstreaming was done, since we had at that time switched
to using 16MB huge pages to map the kernel.

Signed-off-by: default avatarChris Metcalf <cmetcalf@mellanox.com>
parent 18bfd3e6

arch/tile/include/asm/cache.h

+2 −5
Original line number Diff line number Diff line
@@ -50,18 +50,15 @@ 


/*

 * Originally we used small TLB pages for kernel data and grouped some

 * things together as "write once", enforcing the property at the end

 * things together as ro-after-init, enforcing the property at the end

 * of initialization by making those pages read-only and non-coherent.

 * This allowed better cache utilization since cache inclusion did not

 * need to be maintained.  However, to do this requires an extra TLB

 * entry, which on balance is more of a performance hit than the

 * non-coherence is a performance gain, so we now just make "read

 * mostly" and "write once" be synonyms.  We keep the attribute

 * mostly" and "ro-after-init" be synonyms.  We keep the attribute

 * separate in case we change our minds at a future date.

 */

#define __write_once __read_mostly



/* __ro_after_init is the generic name for the tile arch __write_once. */

#define __ro_after_init __read_mostly



#endif /* _ASM_TILE_CACHE_H */

arch/tile/include/asm/sections.h

+0 −3
Original line number Diff line number Diff line
@@ -19,9 +19,6 @@ 


#include <asm-generic/sections.h>



/* Write-once data is writable only till the end of initialization. */

extern char __w1data_begin[], __w1data_end[];



extern char vdso_start[], vdso_end[];

#ifdef CONFIG_COMPAT

extern char vdso32_start[], vdso32_end[];

arch/tile/kernel/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static int pci_probe = 1; 
 * This flag tells if the platform is TILEmpower that needs

 * special configuration for the PLX switch chip.

 */

int __write_once tile_plx_gen1;

int __ro_after_init tile_plx_gen1;



static struct pci_controller controllers[TILE_NUM_PCIE];

static int num_controllers;

arch/tile/kernel/setup.c

+9 −9
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ 
static inline int ABS(int x) { return x >= 0 ? x : -x; }



/* Chip information */

char chip_model[64] __write_once;

char chip_model[64] __ro_after_init;



#ifdef CONFIG_VT

struct screen_info screen_info;
@@ -97,17 +97,17 @@ int node_controller[MAX_NUMNODES] = { [0 ... MAX_NUMNODES-1] = -1 }; 
#ifdef CONFIG_HIGHMEM

/* Map information from VAs to PAs */

unsigned long pbase_map[1 << (32 - HPAGE_SHIFT)]

  __write_once __attribute__((aligned(L2_CACHE_BYTES)));

  __ro_after_init __attribute__((aligned(L2_CACHE_BYTES)));

EXPORT_SYMBOL(pbase_map);



/* Map information from PAs to VAs */

void *vbase_map[NR_PA_HIGHBIT_VALUES]

  __write_once __attribute__((aligned(L2_CACHE_BYTES)));

  __ro_after_init __attribute__((aligned(L2_CACHE_BYTES)));

EXPORT_SYMBOL(vbase_map);

#endif



/* Node number as a function of the high PA bits */

int highbits_to_node[NR_PA_HIGHBIT_VALUES] __write_once;

int highbits_to_node[NR_PA_HIGHBIT_VALUES] __ro_after_init;

EXPORT_SYMBOL(highbits_to_node);



static unsigned int __initdata maxmem_pfn = -1U;
@@ -844,11 +844,11 @@ static void __init zone_sizes_init(void) 
#ifdef CONFIG_NUMA



/* which logical CPUs are on which nodes */

struct cpumask node_2_cpu_mask[MAX_NUMNODES] __write_once;

struct cpumask node_2_cpu_mask[MAX_NUMNODES] __ro_after_init;

EXPORT_SYMBOL(node_2_cpu_mask);



/* which node each logical CPU is on */

char cpu_2_node[NR_CPUS] __write_once __attribute__((aligned(L2_CACHE_BYTES)));

char cpu_2_node[NR_CPUS] __ro_after_init __attribute__((aligned(L2_CACHE_BYTES)));

EXPORT_SYMBOL(cpu_2_node);



/* Return cpu_to_node() except for cpus not yet assigned, which return -1 */
@@ -1269,7 +1269,7 @@ static void __init validate_va(void) 
 * cpus plus any other cpus that are willing to share their cache.

 * It is set by hv_inquire_tiles(HV_INQ_TILES_LOTAR).

 */

struct cpumask __write_once cpu_lotar_map;

struct cpumask __ro_after_init cpu_lotar_map;

EXPORT_SYMBOL(cpu_lotar_map);



/*
@@ -1291,7 +1291,7 @@ EXPORT_SYMBOL(hash_for_home_map); 
 * cache, those tiles will only appear in cpu_lotar_map, NOT in

 * cpu_cacheable_map, as they are a special case.

 */

struct cpumask __write_once cpu_cacheable_map;

struct cpumask __ro_after_init cpu_cacheable_map;

EXPORT_SYMBOL(cpu_cacheable_map);



static __initdata struct cpumask disabled_map;
@@ -1506,7 +1506,7 @@ void __init setup_arch(char **cmdline_p) 
 * Set up per-cpu memory.

 */



unsigned long __per_cpu_offset[NR_CPUS] __write_once;

unsigned long __per_cpu_offset[NR_CPUS] __ro_after_init;

EXPORT_SYMBOL(__per_cpu_offset);



static size_t __initdata pfn_offset[MAX_NUMNODES] = { 0 };

arch/tile/kernel/smp.c

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
 * We write to width and height with a single store in head_NN.S,

 * so make the variable aligned to "long".

 */

HV_Topology smp_topology __write_once __aligned(sizeof(long));

HV_Topology smp_topology __ro_after_init __aligned(sizeof(long));

EXPORT_SYMBOL(smp_topology);



#if CHIP_HAS_IPI()

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