Commit d9b98f5f authored Dec 21, 2010 by Benoit Cousson Committed by Paul Walmsley Dec 21, 2010

OMAP4: clock data: Add control for pad_clks_ck and slimbus_clk



The gating of pad_clks and slimbus_ck is controlled by the PRCM, but
since the clock source is external, this is the SW responsability
to gate / un-gate it when the mcpdm or slimbus module need to be used.
There is no autogating possible with such external clock.

Add SW control to enable / disable this SW gating in the pad_clks_ck
and slimbus_clk clock node.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>

parent 596efe47

arch/arm/mach-omap2/clock44xx_data.c

+6 −2

Original line number	Diff line number	Diff line
		@@ -53,7 +53,9 @@ static struct clk extalt_clkin_ck = {
		static struct clk pad_clks_ck = {
		.name = "pad_clks_ck",
		.rate = 12000000,
		.ops = &clkops_null,
		.ops = &clkops_omap2_dflt,
		.enable_reg = OMAP4430_CM_CLKSEL_ABE,
		.enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
		};

		static struct clk pad_slimbus_core_clks_ck = {
		@@ -71,7 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
		static struct clk slimbus_clk = {
		.name = "slimbus_clk",
		.rate = 12000000,
		.ops = &clkops_null,
		.ops = &clkops_omap2_dflt,
		.enable_reg = OMAP4430_CM_CLKSEL_ABE,
		.enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
		};

		static struct clk sys_32k_ck = {

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