Commit d8f58409 authored Nov 25, 2018 by Dmitry Osipenko Committed by Thierry Reding Jan 16, 2019

ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30



The DRAM refresh-interval is getting erroneously set to "1" on exiting
from memory self-refreshing mode. The clobbered interval causes the
"refresh request overflow timeout" error raised by the External Memory
Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20,
but EMC registers are not latched after exiting from self-refreshing mode
on Tegra20 and hence refresh-interval is not altered until an event that
causes registers latching happens.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 82cdfc38

arch/arm/mach-tegra/sleep-tegra20.S

+0 −2

Original line number	Diff line number	Diff line
		@@ -32,7 +32,6 @@

		#define EMC_CFG 0xc
		#define EMC_ADR_CFG 0x10
		#define EMC_REFRESH 0x70
		#define EMC_NOP 0xdc
		#define EMC_SELF_REF 0xe0
		#define EMC_REQ_CTRL 0x2b0
		@@ -397,7 +396,6 @@ padload_done:
		mov r1, #1
		str r1, [r0, #EMC_NOP]
		str r1, [r0, #EMC_NOP]
		str r1, [r0, #EMC_REFRESH]

		emc_device_mask r1, r0

arch/arm/mach-tegra/sleep-tegra30.S

+0 −2

Original line number	Diff line number	Diff line
		@@ -29,7 +29,6 @@
		#define EMC_CFG 0xc
		#define EMC_ADR_CFG 0x10
		#define EMC_TIMING_CONTROL 0x28
		#define EMC_REFRESH 0x70
		#define EMC_NOP 0xdc
		#define EMC_SELF_REF 0xe0
		#define EMC_MRW 0xe8
		@@ -459,7 +458,6 @@ emc_wait_auto_cal_onetime:
		cmp r10, #TEGRA30
		streq r1, [r0, #EMC_NOP]
		streq r1, [r0, #EMC_NOP]
		streq r1, [r0, #EMC_REFRESH]

		emc_device_mask r1, r0

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