Commit 82cdfc38 authored Nov 25, 2018 by Dmitry Osipenko Committed by Thierry Reding Jan 16, 2019

ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+



The memory interface configuration and re-calibration interval are left
unassigned on resume from LP1 because these registers are shadowed and
require latching after being adjusted.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent bfeffd15

arch/arm/mach-tegra/sleep-tegra30.S

+2 −0

Original line number	Diff line number	Diff line
		@@ -521,6 +521,8 @@ zcal_done:
		ldr r1, [r5, #0x0] @ restore EMC_CFG
		str r1, [r0, #EMC_CFG]

		emc_timing_update r1, r0

		/* Tegra114 had dual EMC channel, now config the other one */
		cmp r10, #TEGRA114
		bne __no_dual_emc_chanl

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