Commit d8c61373 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
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drm/amdgpu/gfx: Replace ARRAY_SIZE with size variable 



Replace ARRAY_SIZE with size variables to support
different ASICs.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarYong Zhao <Yong.Zhao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6eed6cc1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+17 −10
Original line number Diff line number Diff line
@@ -4060,6 +4060,13 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 
	unsigned total_size, vgpr_offset, sgpr_offset;

	u64 gpu_addr;



	int compute_dim_x = adev->gfx.config.max_shader_engines *

						adev->gfx.config.max_cu_per_sh *

						adev->gfx.config.max_sh_per_se;

	int sgpr_work_group_size = 5;

	int gpr_reg_size = ARRAY_SIZE(vgpr_init_regs);

	int sec_ded_counter_reg_size = ARRAY_SIZE(sec_ded_counter_registers);



	/* only support when RAS is enabled */

	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))

		return 0;
@@ -4069,11 +4076,11 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 
		return 0;



	total_size =

		((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;

		(gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */

	total_size +=

		((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;

		(gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */

	total_size +=

		((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;

		(gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */

	total_size = ALIGN(total_size, 256);

	vgpr_offset = total_size;

	total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
@@ -4100,7 +4107,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* VGPR */

	/* write the register state for the compute dispatch */

	for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i++) {

	for (i = 0; i < gpr_reg_size; i++) {

		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);

		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs[i])

								- PACKET3_SET_SH_REG_START;
@@ -4116,7 +4123,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* write dispatch packet */

	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);

	ib.ptr[ib.length_dw++] = 0x40*2; /* x */

	ib.ptr[ib.length_dw++] = compute_dim_x; /* x */

	ib.ptr[ib.length_dw++] = 1; /* y */

	ib.ptr[ib.length_dw++] = 1; /* z */

	ib.ptr[ib.length_dw++] =
@@ -4128,7 +4135,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* SGPR1 */

	/* write the register state for the compute dispatch */

	for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i++) {

	for (i = 0; i < gpr_reg_size; i++) {

		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);

		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])

								- PACKET3_SET_SH_REG_START;
@@ -4144,7 +4151,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* write dispatch packet */

	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);

	ib.ptr[ib.length_dw++] = 0xA0*2; /* x */

	ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */

	ib.ptr[ib.length_dw++] = 1; /* y */

	ib.ptr[ib.length_dw++] = 1; /* z */

	ib.ptr[ib.length_dw++] =
@@ -4156,7 +4163,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* SGPR2 */

	/* write the register state for the compute dispatch */

	for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i++) {

	for (i = 0; i < gpr_reg_size; i++) {

		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);

		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])

								- PACKET3_SET_SH_REG_START;
@@ -4172,7 +4179,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* write dispatch packet */

	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);

	ib.ptr[ib.length_dw++] = 0xA0*2; /* x */

	ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */

	ib.ptr[ib.length_dw++] = 1; /* y */

	ib.ptr[ib.length_dw++] = 1; /* z */

	ib.ptr[ib.length_dw++] =
@@ -4198,7 +4205,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 


	/* read back registers to clear the counters */

	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) {

	for (i = 0; i < sec_ded_counter_reg_size; i++) {

		for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) {

			for (k = 0; k < sec_ded_counter_registers[i].instance; k++) {

				gfx_v9_0_select_se_sh(adev, j, 0x0, k);

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