Commit d7f3894f authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

ARM: dts: imx7: Correct mask for GIC PPI interrupts 



The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual
number of CPU cores the interrupt controller is wired to.

i.MX7S contains a single Cortex-A7, hence the second interrupt specifier
cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".

Likewise, i.MX7D contains two Cortex-A7 cores, so it should use
"GIC_CPU_MASK_SIMPLE(2)" instead.

Tested on a imx7s-warp.

Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0c29339d

arch/arm/boot/dts/imx7d.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -24,6 +24,15 @@ 
		};

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupt-parent = <&intc>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

	};



	cpu0_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;
@@ -72,6 +81,18 @@ 
				};

			};

		};



		intc: interrupt-controller@31001000 {

			compatible = "arm,cortex-a7-gic";

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

			#interrupt-cells = <3>;

			interrupt-controller;

			interrupt-parent = <&intc>;

			reg = <0x31001000 0x1000>,

			      <0x31002000 0x2000>,

			      <0x31004000 0x2000>,

			      <0x31006000 0x2000>;

		};

	};

};

arch/arm/boot/dts/imx7s.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -160,10 +160,10 @@ 
	timer {

		compatible = "arm,armv7-timer";

		interrupt-parent = <&intc>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

	};



	soc {
@@ -305,7 +305,7 @@ 


		intc: interrupt-controller@31001000 {

			compatible = "arm,cortex-a7-gic";

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;

			#interrupt-cells = <3>;

			interrupt-controller;

			interrupt-parent = <&intc>;

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