ARM: dts: imx6ul: Correct mask for GIC PPI interrupts (0c29339d) · Commits · 戴 / test

The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to. i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)". Tested on a imx6ul-evk. Signed-off-by:

Fabio Estevam <festevam@gmail.com> Signed-off-by:

Shawn Guo <shawnguo@kernel.org>

arch/arm/boot/dts/imx6ul.dtsi

+5 −5

Original line number	Diff line number	Diff line
		@@ -94,7 +94,7 @@

		intc: interrupt-controller@a01000 {
		compatible = "arm,gic-400", "arm,cortex-a7-gic";
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		@@ -106,10 +106,10 @@

		timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&intc>;
		status = "disabled";
		};

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