Commit d7c6dbc0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-5.9-2' of... 

Merge tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.9, part 2

1. Minor cleanups and fixes of multiple memory controller drivers,
   mostly around code quality and readability,
2. Add Git repository to drivers/memory entry in MAINTAINERS,
3. Allow MIPS jz4780 FUSE driver to probe by removing conflicting memory
   region with jz4780_nemc.

* tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: jz4780_nemc: Only request IO memory the driver will use
  MAINTAINERS: Add Git repository for memory controller drivers
  memory: brcmstb_dpfe: Fix language typo
  memory: samsung: exynos5422-dmc: Correct white space issues
  memory: samsung: exynos-srom: Correct alignment
  memory: pl172: Enclose macro argument usage in parenthesis
  memory: of: Correct kerneldoc
  memory: omap-gpmc: Fix language typo
  memory: omap-gpmc: Correct white space issues
  memory: omap-gpmc: Use 'unsigned int' for consistency
  memory: omap-gpmc: Enclose macro argument usage in parenthesis
  memory: omap-gpmc: Correct kerneldoc
  memory: mvebu-devbus: Align with open parenthesis
  memory: mvebu-devbus: Add missing braces to all arms of if statement
  memory: bt1-l2-ctl: Add blank lines after declarations

Link: https://lore.kernel.org/r/20200729163008.5820-1-krzk@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9c52a264 f046e4a3

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -11089,6 +11089,7 @@ MEMORY CONTROLLER DRIVERS 
M:	Krzysztof Kozlowski <krzk@kernel.org>

L:	linux-kernel@vger.kernel.org

S:	Maintained

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git

F:	Documentation/devicetree/bindings/memory-controllers/

F:	drivers/memory/

































drivers/memory/brcmstb_dpfe.c



+1
−1






























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Diff line








@@ -23,7 +23,7 @@













 *     - BE kernel + LE firmware image















 *     - BE kernel + BE firmware image















 *













 * The DPCU always runs in big endian mode. The firwmare image, however, can













 * The DPCU always runs in big endian mode. The firmware image, however, can















 * be in either format. Also, communication between host CPU and DCPU is















 * always in little endian.















 */

































drivers/memory/bt1-l2-ctl.c



+2
−0






























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@@ -66,6 +66,7 @@ struct l2_ctl_device_attribute {













	struct device_attribute dev_attr;















	enum l2_ctl_stall id;















};





























#define to_l2_ctl_dev_attr(_dev_attr) \















	container_of(_dev_attr, struct l2_ctl_device_attribute, dev_attr)


























@@ -242,6 +243,7 @@ static ssize_t l2_ctl_latency_store(struct device *dev,





























	return count;















}





























static L2_CTL_ATTR_RW(l2_ws_latency, l2_ctl_latency, L2_WS_STALL);















static L2_CTL_ATTR_RW(l2_tag_latency, l2_ctl_latency, L2_TAG_STALL);















static L2_CTL_ATTR_RW(l2_data_latency, l2_ctl_latency, L2_DATA_STALL);

































drivers/memory/jz4780-nemc.c



+16
−1






























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@@ -8,6 +8,7 @@





























#include <linux/clk.h>















#include <linux/init.h>













#include <linux/io.h>















#include <linux/math64.h>















#include <linux/of.h>















#include <linux/of_address.h>









@@ -22,6 +23,8 @@













#define NEMC_SMCRn(n)		(0x14 + (((n) - 1) * 4))















#define NEMC_NFCSR		0x50





























#define NEMC_REG_LEN		0x54





























#define NEMC_SMCR_SMT		BIT(0)















#define NEMC_SMCR_BW_SHIFT	6















#define NEMC_SMCR_BW_MASK	(0x3 << NEMC_SMCR_BW_SHIFT)










@@ -288,7 +291,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev)













	nemc->dev = dev;































	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);













	nemc->base = devm_ioremap_resource(dev, res);



























	/*













	 * The driver currently only uses the registers up to offset













	 * NEMC_REG_LEN. Since the EFUSE registers are in the middle of the













	 * NEMC registers, we only request the registers we will use for now;













	 * that way the EFUSE driver can probe too.













	 */













	if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {













		dev_err(dev, "unable to request I/O memory region\n");













		return -EBUSY;













	}



























	nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);















	if (IS_ERR(nemc->base)) {















		dev_err(dev, "failed to get I/O memory\n");















		return PTR_ERR(nemc->base);

































drivers/memory/mvebu-devbus.c



+10
−10






























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Diff line








@@ -124,11 +124,11 @@ static int devbus_get_timing_params(struct devbus *devbus,













	 * The bus width is encoded into the register as 0 for 8 bits,















	 * and 1 for 16 bits, so we do the necessary conversion here.















	 */













	if (r->bus_width == 8)













	if (r->bus_width == 8) {















		r->bus_width = 0;













	else if (r->bus_width == 16)













	} else if (r->bus_width == 16) {















		r->bus_width = 1;













	else {













	} else {















		dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);















		return -EINVAL;















	}









































































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