Commit d6fb02f0 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

clk: imx: imx8mq: fix a53 cpu clock 



The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which violates the CCM.

There is a CORE_SEL slice before A53 core, we need to configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.

The A53 CCM clk root should only be used when need to change ARM PLL
frequency.

Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clock

Fixes: db27e40b ("clk: imx8mq: Add the missing ARM clock")
Reviewed-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent c267bd44

drivers/clk/imx/clk-imx8mq.c

+12 −4
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", }; 
static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",

					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };



static const char * const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };



static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",

					"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
@@ -425,6 +427,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MQ_CLK_GPU_SHADER_CG] = hws[IMX8MQ_CLK_GPU_SHADER];

	hws[IMX8MQ_CLK_GPU_SHADER_DIV] = hws[IMX8MQ_CLK_GPU_SHADER];



	/* CORE SEL */

	hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels), CLK_IS_CRITICAL);



	/* BUS */

	hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);

	hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
@@ -588,11 +593,14 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MQ_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc_25m", 1, 8);

	hws[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);



	hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",

					   hws[IMX8MQ_CLK_A53_DIV]->clk,

					   hws[IMX8MQ_CLK_A53_SRC]->clk,

	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC], hws[IMX8MQ_SYS1_PLL_800M]);

	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE], hws[IMX8MQ_ARM_PLL_OUT]);



	hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",

					   hws[IMX8MQ_CLK_A53_CORE]->clk,

					   hws[IMX8MQ_CLK_A53_CORE]->clk,

					   hws[IMX8MQ_ARM_PLL_OUT]->clk,

					   hws[IMX8MQ_SYS1_PLL_800M]->clk);

					   hws[IMX8MQ_CLK_A53_DIV]->clk);



	imx_check_clk_hws(hws, IMX8MQ_CLK_END);

include/dt-bindings/clock/imx8mq-clock.h

+3 −1
Original line number Diff line number Diff line
@@ -429,6 +429,8 @@ 
#define IMX8MQ_CLK_M4_CORE			287

#define IMX8MQ_CLK_VPU_CORE			288



#define IMX8MQ_CLK_END				289

#define IMX8MQ_CLK_A53_CORE			289



#define IMX8MQ_CLK_END				290



#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */

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