drm/amd/display: fix underflow on boot (d5ca5fdb) · Commits · 戴 / test

[Why] New seamless boot sequence introduced a bug where front end is disabled without blanking otg. [How] Adjust the condition of blanking otg to match seamless boot. Signed-off-by:

Eric Yang <Eric.Yang2@amd.com> Reviewed-by:

Anthony Koo <Anthony.Koo@amd.com> Acked-by:

Leo Li <sunpeng.li@amd.com> Acked-by:

Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+2 −4

Original line number	Diff line number	Diff line
		@@ -979,16 +979,14 @@ static void dcn10_init_pipes(struct dc dc, struct dc_state context)
		* to non-preferred front end. If pipe_ctx->stream is not NULL,
		* we will use the pipe, so don't disable
		*/
		if (pipe_ctx->stream != NULL)
		if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
		continue;

		if (tg->funcs->is_tg_enabled(tg))
		tg->funcs->lock(tg);

		/* Blank controller using driver code instead of
		* command table.
		*/
		if (tg->funcs->is_tg_enabled(tg)) {
		tg->funcs->lock(tg);
		tg->funcs->set_blank(tg, true);
		hwss_wait_for_blank_complete(tg);
		}

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