Commit 15ae3b28 authored Mar 25, 2019 by Anthony Koo Committed by Alex Deucher Apr 10, 2019

drm/amd/display: disable link before changing link settings



[Why]
If link is already enabled at a different rate (for example 5.4 Gbps)
then calling VBIOS command table to switch to a new rate
(for example 2.7 Gbps) will not take effect.
This can lead to link training failure to occur.

[How]
If the requested link rate is different than the current link rate,
the link must be disabled in order to re-enable at the new
link rate.

In today's logic it is currently only impacting eDP since DP
connection types will always disable the link during display
detection, when initial link verification occurs.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent c85fc65e

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -1396,6 +1396,15 @@ static enum dc_status enable_link_dp(
		/* get link settings for video mode timing */
		decide_link_settings(stream, &link_settings);

		/* If link settings are different than current and link already enabled
		* then need to disable before programming to new rate.
		*/
		if (link->link_status.link_active &&
		(link->cur_link_settings.lane_count != link_settings.lane_count \|\|
		link->cur_link_settings.link_rate != link_settings.link_rate)) {
		dp_disable_link_phy(link, pipe_ctx->stream->signal);
		}

		pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
		link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
		state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);

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