Commit d51dc613 authored by Jiansong Chen's avatar Jiansong Chen Committed by Alex Deucher
Browse files

drm/amd/powerplay: set VCN1 pg only for sienna_cichlid 



navy_flounder has one VCN instance, and the work around
is to avoid smu reponse error when setting VCN1 pg for
the chip. It is preferred VCN0 and VCN1 are separated
for the pg setting so better power efficiency can be
achieved.

Signed-off-by: default avatarJiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a6c5308f

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+14 −6
Original line number Diff line number Diff line
@@ -826,6 +826,8 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl 
{

	struct smu_power_context *smu_power = &smu->smu_power;

	struct smu_power_gate *power_gate = &smu_power->power_gate;

	struct amdgpu_device *adev = smu->adev;



	int ret = 0;



	if (enable) {
@@ -834,20 +836,26 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl 
			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);

			if (ret)

				return ret;

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL);

			if (adev->asic_type == CHIP_SIENNA_CICHLID) {

				ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,

								  0x10000, NULL);

				if (ret)

					return ret;

			}

		}

		power_gate->vcn_gated = false;

	} else {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);

			if (ret)

				return ret;

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL);

			if (adev->asic_type == CHIP_SIENNA_CICHLID) {

				ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,

								  0x10000, NULL);

				if (ret)

					return ret;

			}

		}

		power_gate->vcn_gated = true;

	}

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