drm/amd/display: add DC support for navy flounder (a6c5308f) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -2808,6 +2808,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
		#endif
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		case CHIP_SIENNA_CICHLID:
		case CHIP_NAVY_FLOUNDER:
		#endif
		return amdgpu_dc != 0;
		#endif

drivers/gpu/drm/amd/amdgpu/nv.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -534,6 +534,10 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
		if (adev->enable_virtual_display \|\| amdgpu_sriov_vf(adev))
		amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
		#if defined(CONFIG_DRM_AMD_DC)
		else if (amdgpu_device_has_dc_support(adev))
		amdgpu_device_ip_block_add(adev, &dm_ip_block);
		#endif
		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -1085,6 +1085,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
		case CHIP_RENOIR:
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		case CHIP_SIENNA_CICHLID:
		case CHIP_NAVY_FLOUNDER:
		#endif
		return 0;
		case CHIP_NAVI12:
		@@ -1184,6 +1185,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
		break;
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		case CHIP_SIENNA_CICHLID:
		case CHIP_NAVY_FLOUNDER:
		dmub_asic = DMUB_ASIC_DCN30;
		fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
		break;
		@@ -3230,6 +3232,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
		case CHIP_RENOIR:
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		case CHIP_SIENNA_CICHLID:
		case CHIP_NAVY_FLOUNDER:
		#endif
		if (dcn10_register_irq_handlers(dm->adev)) {
		DRM_ERROR("DM: Failed to initialize IRQ\n");
		@@ -3387,6 +3390,7 @@ static int dm_early_init(void *handle)
		case CHIP_NAVI12:
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		case CHIP_SIENNA_CICHLID:
		case CHIP_NAVY_FLOUNDER:
		#endif
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		@@ -3710,6 +3714,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
		adev->asic_type == CHIP_NAVI12 \|\|
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		adev->asic_type == CHIP_SIENNA_CICHLID \|\|
		adev->asic_type == CHIP_NAVY_FLOUNDER \|\|
		#endif
		adev->asic_type == CHIP_RENOIR \|\|
		adev->asic_type == CHIP_RAVEN) {
		@@ -3731,9 +3736,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
		tiling_info->gfx9.shaderEnable = 1;

		#ifdef CONFIG_DRM_AMD_DC_DCN3_0
		if (adev->asic_type == CHIP_SIENNA_CICHLID)
		if (adev->asic_type == CHIP_SIENNA_CICHLID \|\|
		adev->asic_type == CHIP_NAVY_FLOUNDER)
		tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

		#endif
		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
		plane_size, tiling_info,

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