Commit d506a65d authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Catch GTT fault errors for gen11+ planes 



Gen11+ has more hardware planes than gen9 so we need to test additional
pipe interrupt register bits to recognize any GTT faults that happen on
these extra planes.

Bspec: 50335
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191008211716.8391-1-matthew.d.roper@intel.com
parent 772d1dea

drivers/gpu/drm/i915/i915_irq.c

+3 −1
Original line number Diff line number Diff line
@@ -2597,7 +2597,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 


static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)

{

	if (INTEL_GEN(dev_priv) >= 9)

	if (INTEL_GEN(dev_priv) >= 11)

		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;

	else if (INTEL_GEN(dev_priv) >= 9)

		return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;

	else

		return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -7391,6 +7391,9 @@ enum { 
#define  GEN8_PIPE_VSYNC		(1 << 1)

#define  GEN8_PIPE_VBLANK		(1 << 0)

#define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)

#define  GEN11_PIPE_PLANE7_FAULT	(1 << 22)

#define  GEN11_PIPE_PLANE6_FAULT	(1 << 21)

#define  GEN11_PIPE_PLANE5_FAULT	(1 << 20)

#define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)

#define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)

#define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
@@ -7410,6 +7413,11 @@ enum { 
	 GEN9_PIPE_PLANE3_FAULT | \

	 GEN9_PIPE_PLANE2_FAULT | \

	 GEN9_PIPE_PLANE1_FAULT)

#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \

	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \

	 GEN11_PIPE_PLANE7_FAULT | \

	 GEN11_PIPE_PLANE6_FAULT | \

	 GEN11_PIPE_PLANE5_FAULT)



#define GEN8_DE_PORT_ISR _MMIO(0x44440)

#define GEN8_DE_PORT_IMR _MMIO(0x44444)

CRA Git | Maintained and supported by SUSTech CRA and CCSE