Commit d31a408f authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'ux500-dt-for-v3.13-3' of... 

Merge tag 'ux500-dt-for-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt

From Linus Walleij:
Five incremental device tree patches around the clock handling,
and adding SSP/SPI devices to the device tree.

* tag 'ux500-dt-for-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson

:
  ARM: ux500: register all SSP and SPI blocks
  ARM: ux500: fix I2C4 clock bit
  ARM: ux500: fix clock for GPIO blocks 6 and 7
  clk: ux500: fix erroneous bit assignment
  ARM: ux500: fix clock for GPIO block 8

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 17761fc8 6e1484c2

arch/arm/boot/dts/ste-dbx5x0.dtsi

+78 −5
Original line number Diff line number Diff line
@@ -197,7 +197,7 @@ 
			#gpio-cells = <2>;

			gpio-bank = <6>;



			clocks = <&prcc_pclk 2 1>;

			clocks = <&prcc_pclk 2 11>;

		};



		gpio7: gpio@8011e080 {
@@ -212,7 +212,7 @@ 
			#gpio-cells = <2>;

			gpio-bank = <7>;



			clocks = <&prcc_pclk 2 1>;

			clocks = <&prcc_pclk 2 11>;

		};



		gpio8: gpio@a03fe000 {
@@ -227,7 +227,7 @@ 
			#gpio-cells = <2>;

			gpio-bank = <8>;



			clocks = <&prcc_pclk 6 1>;

			clocks = <&prcc_pclk 5 1>;

		};



		pinctrl {
@@ -694,7 +694,7 @@ 


			clock-frequency = <400000>;



			clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 9>;

			clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;

			clock-names = "i2cclk", "apb_pclk";

		};
@@ -704,7 +704,80 @@ 
			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

			clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;

			clock-names = "ssp0clk", "apb_pclk";

			dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */

			       <&dma 8 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		ssp@80003000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80003000 0x1000>;

			interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;

			clock-names = "ssp1clk", "apb_pclk";

			dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */

			       <&dma 9 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@8011a000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x8011a000 0x1000>;

			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;

			clock-names = "spi0clk", "apb_pclk";

			dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */

			       <&dma 0 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@80112000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80112000 0x1000>;

			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;

			clock-names = "spi1clk", "apb_pclk";

			dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */

			       <&dma 35 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@80111000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80111000 0x1000>;

			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;

			clock-names = "spi2clk", "apb_pclk";

			dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */

			       <&dma 33 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@80129000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80129000 0x1000>;

			interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;

			clock-names = "spi3clk", "apb_pclk";

			dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */

			       <&dma 40 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		uart@80120000 {

drivers/clk/ux500/u8500_of_clk.c

+1 −1
Original line number Diff line number Diff line
@@ -339,7 +339,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 


	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,

				BIT(11), 0);

	PRCC_PCLK_STORE(clk, 2, 1);

	PRCC_PCLK_STORE(clk, 2, 11);



	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,

				BIT(12), 0);

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