Commit 6e1484c2 authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ux500: register all SSP and SPI blocks 



This adds the SSP and SPI blocks to the device tree and makes
them active. Only this way can their clocks be properly gated
off at boot.

Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 72b3e249

arch/arm/boot/dts/ste-dbx5x0.dtsi

+74 −1
Original line number Diff line number Diff line
@@ -704,7 +704,80 @@ 
			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

			clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;

			clock-names = "ssp0clk", "apb_pclk";

			dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */

			       <&dma 8 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		ssp@80003000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80003000 0x1000>;

			interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;

			clock-names = "ssp1clk", "apb_pclk";

			dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */

			       <&dma 9 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@8011a000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x8011a000 0x1000>;

			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;

			clock-names = "spi0clk", "apb_pclk";

			dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */

			       <&dma 0 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@80112000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80112000 0x1000>;

			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;

			clock-names = "spi1clk", "apb_pclk";

			dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */

			       <&dma 35 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@80111000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80111000 0x1000>;

			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;

			clock-names = "spi2clk", "apb_pclk";

			dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */

			       <&dma 33 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		spi@80129000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80129000 0x1000>;

			interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			/* Same clock wired to kernel and pclk */

			clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;

			clock-names = "spi3clk", "apb_pclk";

			dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */

			       <&dma 40 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";

		};



		uart@80120000 {

CRA Git | Maintained and supported by SUSTech CRA and CCSE