clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll (d28b503c) · Commits · 戴 / test

drivers/clk/qcom/clk-alpha-pll.c

+26 −2

Original line number	Diff line number	Diff line
		@@ -143,6 +143,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
		#define TRION_PLL_CAL_VAL 0x44
		#define TRION_PCAL_DONE BIT(26)

		/* LUCID PLL specific settings and offsets */
		#define LUCID_PCAL_DONE BIT(27)

		#define pll_alpha_width(p) \
		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
		ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
		@@ -1447,7 +1450,7 @@ EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
		* The TRION PLL requires a power-on self-calibration which happens when the
		* PLL comes out of reset. Calibrate in case it is not completed.
		*/
		static int alpha_pll_trion_prepare(struct clk_hw *hw)
		static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 regval;
		@@ -1455,7 +1458,7 @@ static int alpha_pll_trion_prepare(struct clk_hw *hw)

		/* Return early if calibration is not needed. */
		regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
		if (regval & TRION_PCAL_DONE)
		if (regval & pcal_done)
		return 0;

		/* On/off to calibrate */
		@@ -1466,6 +1469,16 @@ static int alpha_pll_trion_prepare(struct clk_hw *hw)
		return ret;
		}

		static int alpha_pll_trion_prepare(struct clk_hw *hw)
		{
		return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
		}

		static int alpha_pll_lucid_prepare(struct clk_hw *hw)
		{
		return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
		}

		static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long prate)
		{
		@@ -1529,6 +1542,17 @@ const struct clk_ops clk_alpha_pll_trion_ops = {
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = alpha_pll_trion_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);

		const struct clk_ops clk_alpha_pll_lucid_ops = {
		.prepare = alpha_pll_lucid_prepare,
		.enable = clk_trion_pll_enable,
		.disable = clk_trion_pll_disable,
		.is_enabled = clk_trion_pll_is_enabled,
		.recalc_rate = clk_trion_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = alpha_pll_trion_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);

		const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {

drivers/clk/qcom/clk-alpha-pll.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -138,7 +138,7 @@ extern const struct clk_ops clk_alpha_pll_trion_ops;
		extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
		extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;

		#define clk_alpha_pll_lucid_ops clk_alpha_pll_trion_ops
		extern const struct clk_ops clk_alpha_pll_lucid_ops;
		#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
		extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;

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