Commit 0b014894 authored by Jonathan Marek's avatar Jonathan Marek Committed by Stephen Boyd
Browse files

clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid 



Fixed ops were already identical, this adds support for non-fixed ops by
sharing between trion and lucid.

This also changes the names for trion ops to be consistent with the rest.

Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for
lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Tested-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-4-jonathan@marek.ca


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent c8b9002f

drivers/clk/qcom/clk-alpha-pll.c

+17 −41
Original line number Diff line number Diff line
@@ -101,21 +101,6 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_FRAC] = 0x38,

	},

	[CLK_ALPHA_PLL_TYPE_TRION] = {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_CAL_L_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,

		[PLL_OFF_USER_CTL_U] = 0x10,

		[PLL_OFF_USER_CTL_U1] = 0x14,

		[PLL_OFF_CONFIG_CTL] = 0x18,

		[PLL_OFF_CONFIG_CTL_U] = 0x1c,

		[PLL_OFF_CONFIG_CTL_U1] = 0x20,

		[PLL_OFF_TEST_CTL] = 0x24,

		[PLL_OFF_TEST_CTL_U] = 0x28,

		[PLL_OFF_STATUS] = 0x30,

		[PLL_OFF_OPMODE] = 0x38,

		[PLL_OFF_ALPHA_VAL] = 0x40,

	},

	[CLK_ALPHA_PLL_TYPE_LUCID] =  {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_CAL_L_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,
@@ -154,9 +139,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define PLL_OUT_MASK		0x7

#define PLL_RATE_MARGIN		500



/* LUCID PLL specific settings and offsets */

#define LUCID_PLL_CAL_VAL	0x44

#define LUCID_PCAL_DONE		BIT(26)

/* TRION PLL specific settings and offsets */

#define TRION_PLL_CAL_VAL	0x44

#define TRION_PCAL_DONE		BIT(26)



#define pll_alpha_width(p)					\

		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
@@ -910,14 +895,14 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { 
};

EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);



const struct clk_ops clk_trion_fixed_pll_ops = {

const struct clk_ops clk_alpha_pll_fixed_trion_ops = {

	.enable = clk_trion_pll_enable,

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

};

EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);



static unsigned long

clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
@@ -1337,12 +1322,12 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 
				  val << PLL_POST_DIV_SHIFT);

}



const struct clk_ops clk_trion_pll_postdiv_ops = {

const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {

	.recalc_rate = clk_trion_pll_postdiv_recalc_rate,

	.round_rate = clk_trion_pll_postdiv_round_rate,

	.set_rate = clk_trion_pll_postdiv_set_rate,

};

EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);



static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,

				unsigned long rate, unsigned long *prate)
@@ -1397,13 +1382,13 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 
 * @regmap: register map

 * @config: configuration to apply for pll

 */

void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config)

{

	if (config->l)

		regmap_write(regmap, PLL_L_VAL(pll), config->l);



	regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);

	regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);



	if (config->alpha)

		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
@@ -1456,13 +1441,13 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
	/* Place the PLL in STANDBY mode */

	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);

}

EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);

EXPORT_SYMBOL_GPL(clk_trion_pll_configure);



/*

 * The Lucid PLL requires a power-on self-calibration which happens when the

 * The TRION PLL requires a power-on self-calibration which happens when the

 * PLL comes out of reset. Calibrate in case it is not completed.

 */

static int alpha_pll_lucid_prepare(struct clk_hw *hw)

static int alpha_pll_trion_prepare(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 regval;
@@ -1470,7 +1455,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) 


	/* Return early if calibration is not needed. */

	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);

	if (regval & LUCID_PCAL_DONE)

	if (regval & TRION_PCAL_DONE)

		return 0;



	/* On/off to calibrate */
@@ -1481,7 +1466,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) 
	return ret;

}



static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,

static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@@ -1535,26 +1520,17 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



const struct clk_ops clk_alpha_pll_lucid_ops = {

	.prepare = alpha_pll_lucid_prepare,

const struct clk_ops clk_alpha_pll_trion_ops = {

	.prepare = alpha_pll_trion_prepare,

	.enable = clk_trion_pll_enable,

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_set_rate,

	.set_rate = alpha_pll_trion_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);



const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {

	.enable = clk_trion_pll_enable,

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);



const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {

	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

drivers/clk/qcom/clk-alpha-pll.h

+11 −6
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_BRAMMO,

	CLK_ALPHA_PLL_TYPE_FABIA,

	CLK_ALPHA_PLL_TYPE_TRION,

	CLK_ALPHA_PLL_TYPE_LUCID,

	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,

	CLK_ALPHA_PLL_TYPE_MAX,

};
@@ -134,18 +134,23 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops; 
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;

extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;



extern const struct clk_ops clk_alpha_pll_lucid_ops;

extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;

extern const struct clk_ops clk_alpha_pll_trion_ops;

extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;

extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;



#define clk_alpha_pll_lucid_ops clk_alpha_pll_trion_ops

#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops

extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);

void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);

#define clk_lucid_pll_configure(pll, regmap, config) \

	clk_trion_pll_configure(pll, regmap, config)





extern const struct clk_ops clk_trion_fixed_pll_ops;

extern const struct clk_ops clk_trion_pll_postdiv_ops;



#endif

drivers/clk/qcom/gcc-sm8150.c

+4 −4
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static struct clk_alpha_pll gpll0 = { 
				.name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_trion_fixed_pll_ops,

			.ops = &clk_alpha_pll_fixed_trion_ops,

		},

	},

};
@@ -79,7 +79,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { 
			.hw = &gpll0.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_trion_pll_postdiv_ops,

		.ops = &clk_alpha_pll_postdiv_trion_ops,

	},

};
@@ -98,7 +98,7 @@ static struct clk_alpha_pll gpll7 = { 
				.name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_trion_fixed_pll_ops,

			.ops = &clk_alpha_pll_fixed_trion_ops,

		},

	},

};
@@ -118,7 +118,7 @@ static struct clk_alpha_pll gpll9 = { 
				.name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_trion_fixed_pll_ops,

			.ops = &clk_alpha_pll_fixed_trion_ops,

		},

	},

};

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