Commit c8b9002f authored by Jonathan Marek's avatar Jonathan Marek Committed by Stephen Boyd
Browse files

clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL 



0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.

Fixes: 548a9095 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")
Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Tested-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-3-jonathan@marek.ca


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 667f39b5

drivers/clk/qcom/clk-alpha-pll.c

+0 −2
Original line number Diff line number Diff line
@@ -56,7 +56,6 @@ 
#define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])

#define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])

#define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])

#define PLL_CAL_VAL(p)		((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])



const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {

	[CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
@@ -115,7 +114,6 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_STATUS] = 0x30,

		[PLL_OFF_OPMODE] = 0x38,

		[PLL_OFF_ALPHA_VAL] = 0x40,

		[PLL_OFF_CAL_VAL] = 0x44,

	},

	[CLK_ALPHA_PLL_TYPE_LUCID] =  {

		[PLL_OFF_L_VAL] = 0x04,

CRA Git | Maintained and supported by SUSTech CRA and CCSE