Commit d1b8b965 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v4.16-rockchip-dts32fixes-1' of... 

Merge tag 'v4.16-rockchip-dts32fixes-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes

Pull "Rockchip dts32 fixes for 4.16" from Heiko Stübner:

Fix wrong dwmmc tuning clocks that may make probing HS cards fail to
probe and removal of special opps from the phycore boards that may
run the cpu outside the soc-vendor specs.

* tag 'v4.16-rockchip-dts32fixes-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Fix DWMMC clocks
  ARM: dts: rockchip: Remove 1.8 GHz operation point from phycore som
parents c209d25e e78c6371

arch/arm/boot/dts/rk3036.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ 
		max-frequency = <37500000>;

		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,

			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;

		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		resets = <&cru SRST_SDIO>;
@@ -298,7 +298,7 @@ 
		max-frequency = <37500000>;

		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,

			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;

		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		default-sample-phase = <158>;

		disable-wp;

		dmas = <&pdma 12>;

arch/arm/boot/dts/rk322x.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -621,7 +621,7 @@ 
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,

			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;

		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		pinctrl-names = "default";

		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
@@ -634,7 +634,7 @@ 
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,

			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;

		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		pinctrl-names = "default";

		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
@@ -649,7 +649,7 @@ 
		max-frequency = <37500000>;

		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,

			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;

		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		bus-width = <8>;

		default-sample-phase = <158>;

		fifo-depth = <0x100>;

arch/arm/boot/dts/rk3288-phycore-som.dtsi

+0 −20
Original line number Diff line number Diff line
@@ -110,26 +110,6 @@ 
	};

};



&cpu0 {

	cpu0-supply = <&vdd_cpu>;

	operating-points = <

		/* KHz    uV */

		1800000	1400000

		1608000	1350000

		1512000 1300000

		1416000 1200000

		1200000 1100000

		1008000 1050000

		 816000 1000000

		 696000  950000

		 600000  900000

		 408000  900000

		 312000  900000

		 216000  900000

		 126000  900000

	>;

};



&emmc {

	status = "okay";

	bus-width = <8>;

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