Commit d1ab5b27 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/vdsc: use intel_de_*() functions for register access 



The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/735389bfa1f9c4be8080f3187ea1dbde308d1ce2.1579871655.git.jani.nikula@intel.com
parent d49e857c

drivers/gpu/drm/i915/display/intel_vdsc.c

+249 −164
Original line number Diff line number Diff line
@@ -520,17 +520,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		pps_val |= DSC_VBR_ENABLE;

	DRM_INFO("PPS0 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),

				       pps_val);

	}
@@ -539,17 +544,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);

	DRM_INFO("PPS1 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),

				       pps_val);

	}
@@ -559,17 +569,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);

	DRM_INFO("PPS2 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),

				       pps_val);

	}
@@ -579,17 +594,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);

	DRM_INFO("PPS3 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),

				       pps_val);

	}
@@ -599,17 +619,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);

	DRM_INFO("PPS4 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),

				       pps_val);

	}
@@ -619,17 +644,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);

	DRM_INFO("PPS5 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),

				       pps_val);

	}
@@ -641,17 +671,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);

	DRM_INFO("PPS6 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),

				       pps_val);

	}
@@ -661,17 +696,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);

	DRM_INFO("PPS7 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),

				       pps_val);

	}
@@ -681,17 +721,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);

	DRM_INFO("PPS8 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),

				       pps_val);

	}
@@ -701,17 +746,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);

	DRM_INFO("PPS9 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);

			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,

				       pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),

				       pps_val);

	}
@@ -723,17 +773,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);

	DRM_INFO("PPS10 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);

			intel_de_write(dev_priv,

				       DSCC_PICTURE_PARAMETER_SET_10, pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),

				       pps_val);

	}
@@ -746,17 +801,22 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
					vdsc_cfg->slice_height);

	DRM_INFO("PPS16 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,

			       pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second

		 * VDSC

		 */

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);

			intel_de_write(dev_priv,

				       DSCC_PICTURE_PARAMETER_SET_16, pps_val);

	} else {

		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);

		intel_de_write(dev_priv,

			       ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),

			       pps_val);

		if (crtc_state->dsc.dsc_split)

			I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),

				       pps_val);

	}
@@ -770,37 +830,45 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
			 rc_buf_thresh_dword[i / 4]);

	}

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);

		I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);

		I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);

		I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);

		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,

			       rc_buf_thresh_dword[0]);

		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,

			       rc_buf_thresh_dword[1]);

		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,

			       rc_buf_thresh_dword[2]);

		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,

			       rc_buf_thresh_dword[3]);

		if (crtc_state->dsc.dsc_split) {

			I915_WRITE(DSCC_RC_BUF_THRESH_0,

			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,

				       rc_buf_thresh_dword[0]);

			I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,

			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,

				       rc_buf_thresh_dword[1]);

			I915_WRITE(DSCC_RC_BUF_THRESH_1,

			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,

				       rc_buf_thresh_dword[2]);

			I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,

			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,

				       rc_buf_thresh_dword[3]);

		}

	} else {

		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),

			       rc_buf_thresh_dword[0]);

		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),

			       rc_buf_thresh_dword[1]);

		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),

			       rc_buf_thresh_dword[2]);

		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),

			       rc_buf_thresh_dword[3]);

		if (crtc_state->dsc.dsc_split) {

			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_BUF_THRESH_0(pipe),

				       rc_buf_thresh_dword[0]);

			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),

				       rc_buf_thresh_dword[1]);

			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_BUF_THRESH_1(pipe),

				       rc_buf_thresh_dword[2]);

			I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),

				       rc_buf_thresh_dword[3]);

		}

	}
@@ -819,73 +887,89 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
			 rc_range_params_dword[i / 2]);

	}

	if (!is_pipe_dsc(crtc_state)) {

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,

			       rc_range_params_dword[0]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,

			       rc_range_params_dword[1]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,

			       rc_range_params_dword[2]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,

			       rc_range_params_dword[3]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,

			       rc_range_params_dword[4]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,

			       rc_range_params_dword[5]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,

			       rc_range_params_dword[6]);

		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,

		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,

			       rc_range_params_dword[7]);

		if (crtc_state->dsc.dsc_split) {

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,

			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,

				       rc_range_params_dword[0]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,

			intel_de_write(dev_priv,

				       DSCC_RC_RANGE_PARAMETERS_0_UDW,

				       rc_range_params_dword[1]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,

			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,

				       rc_range_params_dword[2]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,

			intel_de_write(dev_priv,

				       DSCC_RC_RANGE_PARAMETERS_1_UDW,

				       rc_range_params_dword[3]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,

			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,

				       rc_range_params_dword[4]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,

			intel_de_write(dev_priv,

				       DSCC_RC_RANGE_PARAMETERS_2_UDW,

				       rc_range_params_dword[5]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,

			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,

				       rc_range_params_dword[6]);

			I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,

			intel_de_write(dev_priv,

				       DSCC_RC_RANGE_PARAMETERS_3_UDW,

				       rc_range_params_dword[7]);

		}

	} else {

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),

			       rc_range_params_dword[0]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),

		intel_de_write(dev_priv,

			       ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),

			       rc_range_params_dword[1]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),

			       rc_range_params_dword[2]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),

		intel_de_write(dev_priv,

			       ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),

			       rc_range_params_dword[3]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),

			       rc_range_params_dword[4]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),

		intel_de_write(dev_priv,

			       ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),

			       rc_range_params_dword[5]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),

		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),

			       rc_range_params_dword[6]);

		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),

		intel_de_write(dev_priv,

			       ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),

			       rc_range_params_dword[7]);

		if (crtc_state->dsc.dsc_split) {

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),

				       rc_range_params_dword[0]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),

				       rc_range_params_dword[1]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),

				       rc_range_params_dword[2]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),

				       rc_range_params_dword[3]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),

				       rc_range_params_dword[4]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),

				       rc_range_params_dword[5]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),

				       rc_range_params_dword[6]);

			I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),

			intel_de_write(dev_priv,

				       ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),

				       rc_range_params_dword[7]);

		}

	}
@@ -912,11 +996,11 @@ void intel_dsc_get_config(struct intel_encoder *encoder, 
		return;



	if (!is_pipe_dsc(crtc_state)) {

		dss_ctl1 = I915_READ(DSS_CTL1);

		dss_ctl2 = I915_READ(DSS_CTL2);

		dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);

		dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);

	} else {

		dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe));

		dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe));

		dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));

		dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe));

	}



	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
@@ -930,9 +1014,10 @@ void intel_dsc_get_config(struct intel_encoder *encoder, 


	/* PPS1 */

	if (!is_pipe_dsc(crtc_state))

		val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1);

		val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);

	else

		val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));

		val = intel_de_read(dev_priv,

				    ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));

	vdsc_cfg->bits_per_pixel = val;

	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;

out:
@@ -1013,8 +1098,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, 
		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;

		dss_ctl1_val |= JOINER_ENABLE;

	}

	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);

	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);

	intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);

	intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);

}



void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1035,17 +1120,17 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 
		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);

		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);

	}

	dss_ctl1_val = I915_READ(dss_ctl1_reg);

	dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg);

	if (dss_ctl1_val & JOINER_ENABLE)

		dss_ctl1_val &= ~JOINER_ENABLE;

	I915_WRITE(dss_ctl1_reg, dss_ctl1_val);

	intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);



	dss_ctl2_val = I915_READ(dss_ctl2_reg);

	dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg);

	if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||

	    dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)

		dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |

				  RIGHT_BRANCH_VDSC_ENABLE);

	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);

	intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);



	/* Disable Power wells for VDSC/joining */

	intel_display_power_put_unchecked(dev_priv,

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