Commit d49e857c authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/sprite: use intel_de_*() functions for register access 



The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/722f73a4529808ef7dad51c03c0a3775d8c5b052.1579871655.git.jani.nikula@intel.com
parent c51e7138

drivers/gpu/drm/i915/display/intel_sprite.c

+175 −145
Original line number Diff line number Diff line
@@ -434,14 +434,16 @@ skl_program_scaler(struct intel_plane *plane, 
		uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);

	}



	I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),

	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id),

			  PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);

	I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),

	intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),

			  PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));

	I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),

	intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),

			  PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));

	I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);

	I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);

	intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),

			  (crtc_x << 16) | crtc_y);

	intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),

			  (crtc_w << 16) | crtc_h);

}



/* Preoffset values for YUV to RGB Conversion */
@@ -547,28 +549,37 @@ icl_program_input_csc(struct intel_plane *plane, 
	else

		csc = input_csc_matrix_lr[plane_state->hw.color_encoding];



	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |

		      GOFF(csc[1]));

	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));

	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |

		      GOFF(csc[4]));

	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));

	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |

		      GOFF(csc[7]));

	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));



	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),

			  ROFF(csc[0]) | GOFF(csc[1]));

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),

			  BOFF(csc[2]));

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),

			  ROFF(csc[3]) | GOFF(csc[4]));

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),

			  BOFF(csc[5]));

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),

			  ROFF(csc[6]) | GOFF(csc[7]));

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),

			  BOFF(csc[8]));



	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),

			  PREOFF_YUV_TO_RGB_HI);

	if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)

		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);

		intel_de_write_fw(dev_priv,

				  PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

				  0);

	else

		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

		intel_de_write_fw(dev_priv,

				  PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),

				  PREOFF_YUV_TO_RGB_ME);

	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),

	intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),

			  PREOFF_YUV_TO_RGB_LO);

	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);

	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);

	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);

	intel_de_write_fw(dev_priv,

			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);

	intel_de_write_fw(dev_priv,

			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);

	intel_de_write_fw(dev_priv,

			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);

}



static void
@@ -623,43 +634,48 @@ skl_program_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);

	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);

	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);

	intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);

	intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),

			  (crtc_y << 16) | crtc_x);

	intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),

			  (src_h << 16) | src_w);



	if (INTEL_GEN(dev_priv) < 12)

		aux_dist |= aux_stride;

	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);

	intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);



	if (icl_is_hdr_plane(dev_priv, plane_id))

		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);

		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),

				  plane_state->cus_ctl);



	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);

		intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),

				  plane_color_ctl);



	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))

		icl_program_input_csc(plane, crtc_state, plane_state);



	skl_write_plane_wm(plane, crtc_state);



	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);

	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);

	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);

	intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),

			  key->min_value);

	intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);

	intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);



	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);

	intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),

			  (y << 16) | x);



	if (INTEL_GEN(dev_priv) < 11)

		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),

			      (plane_state->color_plane[1].y << 16) |

			      plane_state->color_plane[1].x);

		intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),

				  (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x);



	/*

	 * The control register self-arms if the plane was previously

	 * disabled. Try to make the plane enable atomic by writing

	 * the control register just before the surface register.

	 */

	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);

	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),

	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),

			  intel_plane_ggtt_offset(plane_state) + surf_addr);



	if (plane_state->scaler_id >= 0)
@@ -693,12 +709,12 @@ skl_disable_plane(struct intel_plane *plane, 
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	if (icl_is_hdr_plane(dev_priv, plane_id))

		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0);

		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);



	skl_write_plane_wm(plane, crtc_state);



	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);

	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}
@@ -718,7 +734,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, 
	if (!wakeref)

		return false;



	ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

	ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;



	*pipe = plane->pipe;
@@ -774,23 +790,36 @@ chv_update_csc(const struct intel_plane_state *plane_state) 
	if (!fb->format->is_yuv)

		return;



	I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));

	I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));

	I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));



	I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));

	I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));

	I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));

	I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));

	I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));



	I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));

	I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));

	I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));



	I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));

	I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));

	I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));

	intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id),

			  SPCSC_OOFF(0) | SPCSC_IOFF(0));

	intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id),

			  SPCSC_OOFF(0) | SPCSC_IOFF(0));

	intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id),

			  SPCSC_OOFF(0) | SPCSC_IOFF(0));



	intel_de_write_fw(dev_priv, SPCSCC01(plane_id),

			  SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));

	intel_de_write_fw(dev_priv, SPCSCC23(plane_id),

			  SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));

	intel_de_write_fw(dev_priv, SPCSCC45(plane_id),

			  SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));

	intel_de_write_fw(dev_priv, SPCSCC67(plane_id),

			  SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));

	intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8]));



	intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id),

			  SPCSC_IMAX(1023) | SPCSC_IMIN(0));

	intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id),

			  SPCSC_IMAX(512) | SPCSC_IMIN(-512));

	intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id),

			  SPCSC_IMAX(512) | SPCSC_IMIN(-512));



	intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id),

			  SPCSC_OMAX(1023) | SPCSC_OMIN(0));

	intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id),

			  SPCSC_OMAX(1023) | SPCSC_OMIN(0));

	intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id),

			  SPCSC_OMAX(1023) | SPCSC_OMIN(0));

}



#define SIN_0 0
@@ -829,9 +858,9 @@ vlv_update_clrc(const struct intel_plane_state *plane_state) 
	}



	/* FIXME these register are single buffered :( */

	I915_WRITE_FW(SPCLRC0(pipe, plane_id),

	intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id),

			  SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));

	I915_WRITE_FW(SPCLRC1(pipe, plane_id),

	intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id),

			  SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));

}
@@ -1019,10 +1048,8 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state) 
	/* FIXME these register are single buffered :( */

	/* The two end points are implicit (0.0 and 1.0) */

	for (i = 1; i < 8 - 1; i++)

		I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1),

			      gamma[i] << 16 |

			      gamma[i] << 8 |

			      gamma[i]);

		intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1),

				  gamma[i] << 16 | gamma[i] << 8 | gamma[i]);

}



static void
@@ -1055,31 +1082,36 @@ vlv_update_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),

	intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),

			  plane_state->color_plane[0].stride);

	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);

	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);

	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),

			  (crtc_y << 16) | crtc_x);

	intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),

			  (crtc_h << 16) | crtc_w);

	intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);



	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)

		chv_update_csc(plane_state);



	if (key->flags) {

		I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);

		I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);

		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);

		intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),

				  key->min_value);

		intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id),

				  key->channel_mask);

		intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id),

				  key->max_value);

	}



	I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);

	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);

	intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);

	intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);



	/*

	 * The control register self-arms if the plane was previously

	 * disabled. Try to make the plane enable atomic by writing

	 * the control register just before the surface register.

	 */

	I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);

	I915_WRITE_FW(SPSURF(pipe, plane_id),

	intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl);

	intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),

			  intel_plane_ggtt_offset(plane_state) + sprsurf_offset);



	vlv_update_clrc(plane_state);
@@ -1099,8 +1131,8 @@ vlv_disable_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);

	I915_WRITE_FW(SPSURF(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}
@@ -1120,7 +1152,7 @@ vlv_plane_get_hw_state(struct intel_plane *plane, 
	if (!wakeref)

		return false;



	ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

	ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;



	*pipe = plane->pipe;
@@ -1424,19 +1456,17 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state) 


	/* FIXME these register are single buffered :( */

	for (i = 0; i < 16; i++)

		I915_WRITE_FW(SPRGAMC(pipe, i),

			      gamma[i] << 20 |

			      gamma[i] << 10 |

			      gamma[i]);



	I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]);

	I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]);

	I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]);

		intel_de_write_fw(dev_priv, SPRGAMC(pipe, i),

				  gamma[i] << 20 | gamma[i] << 10 | gamma[i]);



	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]);

	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]);

	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]);

	i++;



	I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]);

	I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]);

	I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]);

	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]);

	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]);

	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]);

	i++;

}
@@ -1476,25 +1506,27 @@ ivb_update_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);

	I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);

	I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);

	intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),

			  plane_state->color_plane[0].stride);

	intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);

	intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);

	if (IS_IVYBRIDGE(dev_priv))

		I915_WRITE_FW(SPRSCALE(pipe), sprscale);

		intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);



	if (key->flags) {

		I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);

		I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);

		I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);

		intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);

		intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),

				  key->channel_mask);

		intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value);

	}



	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET

	 * register */

	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);

		intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);

	} else {

		I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);

		I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);

		intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);

		intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);

	}



	/*
@@ -1502,8 +1534,8 @@ ivb_update_plane(struct intel_plane *plane, 
	 * disabled. Try to make the plane enable atomic by writing

	 * the control register just before the surface register.

	 */

	I915_WRITE_FW(SPRCTL(pipe), sprctl);

	I915_WRITE_FW(SPRSURF(pipe),

	intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl);

	intel_de_write_fw(dev_priv, SPRSURF(pipe),

			  intel_plane_ggtt_offset(plane_state) + sprsurf_offset);



	ivb_update_gamma(plane_state);
@@ -1521,11 +1553,11 @@ ivb_disable_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(SPRCTL(pipe), 0);

	intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);

	/* Disable the scaler */

	if (IS_IVYBRIDGE(dev_priv))

		I915_WRITE_FW(SPRSCALE(pipe), 0);

	I915_WRITE_FW(SPRSURF(pipe), 0);

		intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);

	intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}
@@ -1544,7 +1576,7 @@ ivb_plane_get_hw_state(struct intel_plane *plane, 
	if (!wakeref)

		return false;



	ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;

	ret =  intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE;



	*pipe = plane->pipe;
@@ -1710,10 +1742,8 @@ static void g4x_update_gamma(const struct intel_plane_state *plane_state) 
	/* FIXME these register are single buffered :( */

	/* The two end points are implicit (0.0 and 1.0) */

	for (i = 1; i < 8 - 1; i++)

		I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1),

			      gamma[i] << 16 |

			      gamma[i] << 8 |

			      gamma[i]);

		intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1),

				  gamma[i] << 16 | gamma[i] << 8 | gamma[i]);

}



static void ilk_sprite_linear_gamma(u16 gamma[17])
@@ -1741,14 +1771,12 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state) 


	/* FIXME these register are single buffered :( */

	for (i = 0; i < 16; i++)

		I915_WRITE_FW(DVSGAMC_ILK(pipe, i),

			      gamma[i] << 20 |

			      gamma[i] << 10 |

			      gamma[i]);



	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]);

	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]);

	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]);

		intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i),

				  gamma[i] << 20 | gamma[i] << 10 | gamma[i]);



	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);

	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);

	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);

	i++;

}
@@ -1788,27 +1816,29 @@ g4x_update_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);

	I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);

	I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);

	I915_WRITE_FW(DVSSCALE(pipe), dvsscale);

	intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),

			  plane_state->color_plane[0].stride);

	intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);

	intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);

	intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);



	if (key->flags) {

		I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);

		I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);

		I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);

		intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);

		intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),

				  key->channel_mask);

		intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value);

	}



	I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);

	I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);

	intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset);

	intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), (y << 16) | x);



	/*

	 * The control register self-arms if the plane was previously

	 * disabled. Try to make the plane enable atomic by writing

	 * the control register just before the surface register.

	 */

	I915_WRITE_FW(DVSCNTR(pipe), dvscntr);

	I915_WRITE_FW(DVSSURF(pipe),

	intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr);

	intel_de_write_fw(dev_priv, DVSSURF(pipe),

			  intel_plane_ggtt_offset(plane_state) + dvssurf_offset);



	if (IS_G4X(dev_priv))
@@ -1829,10 +1859,10 @@ g4x_disable_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	I915_WRITE_FW(DVSCNTR(pipe), 0);

	intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);

	/* Disable the scaler */

	I915_WRITE_FW(DVSSCALE(pipe), 0);

	I915_WRITE_FW(DVSSURF(pipe), 0);

	intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);

	intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}
@@ -1851,7 +1881,7 @@ g4x_plane_get_hw_state(struct intel_plane *plane, 
	if (!wakeref)

		return false;



	ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;

	ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE;



	*pipe = plane->pipe;

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