drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2 (d112ea3c) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+27 −4

Original line number	Diff line number	Diff line
		@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context smu, void buf, size_t size)
		smu_table->power_play_table = smu_table->hardcode_pptable;
		smu_table->power_play_table_size = size;

		/*
		* Special hw_fini action(for Navi1x, the DPMs disablement will be
		* skipped) may be needed for custom pptable uploading.
		*/
		smu->uploading_custom_pp_table = true;

		ret = smu_reset(smu);
		if (ret)
		pr_info("smu reset failed, ret = %d\n", ret);

		smu->uploading_custom_pp_table = false;

		failed:
		mutex_unlock(&smu->mutex);
		return ret;
		@@ -1295,11 +1303,26 @@ static int smu_hw_fini(void *handle)
		return ret;
		}

		/*
		* For custom pptable uploading, skip the DPM features
		* disable process on Navi1x ASICs.
		* - As the gfx related features are under control of
		* RLC on those ASICs. RLC reinitialization will be
		* needed to reenable them. That will cost much more
		* efforts.
		*
		* - SMU firmware can handle the DPM reenablement
		* properly.
		*/
		if (!smu->uploading_custom_pp_table \|\|
		!((adev->asic_type >= CHIP_NAVI10) &&
		(adev->asic_type <= CHIP_NAVI12))) {
		ret = smu_stop_dpms(smu);
		if (ret) {
		pr_warn("Fail to stop Dpms!\n");
		return ret;
		}
		}

		kfree(table_context->driver_pptable);
		table_context->driver_pptable = NULL;

+1 −0

Original line number	Diff line number	Diff line
		@@ -390,6 +390,7 @@ struct smu_context

		uint32_t smc_if_version;

		bool uploading_custom_pp_table;
		};

		struct i2c_adapter;