Commit d09b17f7 authored by Vasanthakumar Thiagarajan's avatar Vasanthakumar Thiagarajan Committed by John W. Linville
Browse files

ath9k: Configure pll control for AR9485 



Signed-off-by: default avatarVasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 47c80de6

drivers/net/wireless/ath/ath9k/hw.c

+6 −1
Original line number Diff line number Diff line
@@ -667,7 +667,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah) 
static void ath9k_hw_init_pll(struct ath_hw *ah,

			      struct ath9k_channel *chan)

{

	u32 pll = ath9k_hw_compute_pll_control(ah, chan);

	u32 pll;



	if (AR_SREV_9485(ah))

		REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);



	pll = ath9k_hw_compute_pll_control(ah, chan);



	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

drivers/net/wireless/ath/ath9k/reg.h

+2 −0
Original line number Diff line number Diff line
@@ -1114,6 +1114,8 @@ enum { 
#define AR_RTC_PLL_CONTROL \

	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)



#define AR_RTC_PLL_CONTROL2	0x703c



#define AR_RTC_PLL_DIV          0x0000001f

#define AR_RTC_PLL_DIV_S        0

#define AR_RTC_PLL_DIV2         0x00000020

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