Commit ce51c2b7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Initial support for SD express card/host

  MMC host:
   - mxc: Convert the driver to DT-only
   - mtk-sd: Add HS400 enhanced strobe support
   - mtk-sd: Add support for the MT8192 SoC variant
   - sdhci-acpi: Allow changing HS200/HS400 driver strength for AMDI0040
   - sdhci-esdhc-imx: Convert the driver to DT-only
   - sdhci-pci-gli: Improve performance for HS400 mode for GL9763E
   - sdhci-pci-gli: Reduce power consumption for GL9755
   - sdhci-xenon: Introduce ACPI support
   - tmio: Fix command error processing
   - tmio: Inform the core about the max_busy_timeout
   - tmio/renesas_sdhi: Support custom calculation of busy-wait time
   - renesas_sdhi: Reset SCC only when available
   - rtsx_pci: Add SD Express mode support for RTS5261
   - rtsx_pci: Various fixes and improvements for RTS5261

  MEMSTICK:
   - Minor fixes/improvements"

* tag 'mmc-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (72 commits)
  dt-bindings: mmc: eliminate yamllint warnings
  mmc: sdhci-xenon: introduce ACPI support
  mmc: sdhci-xenon: use clk only with DT
  mmc: sdhci-xenon: switch to device_* API
  mmc: sdhci-xenon: use match data for controllers variants
  dt-bindings: mmc: Fix xlnx,mio-bank property values for arasan driver
  mmc: renesas_sdhi: populate hook for longer busy_wait
  mmc: tmio: add hook for custom busy_wait calculation
  mmc: tmio: set max_busy_timeout
  dt-bindings: mmc: imx: fix the wrongly dropped imx8qm compatible string
  mmc: sdhci-pci-gli: Disable slow mode in HS400 mode for GL9763E
  mmc: sdhci: Use more concise device_property_read_u64
  memstick: r592: Fix error return in r592_probe()
  mmc: mxc: Convert the driver to DT-only
  mmc: mxs: Remove the unused .id_table
  mmc: sdhci-of-arasan: Fix fall-through warnings for Clang
  mmc: sdhci-pci-gli: Reduce power consumption for GL9755
  mmc: mediatek: depend on COMMON_CLK to fix compile tests
  mmc: pxamci: Fix error return code in pxamci_probe
  mmc: sdhci: Update firmware interface API
  ...
parents 9d0d8867 72b248cf

Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml

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@@ -147,7 +147,7 @@ properties: 


  xlnx,mio-bank:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 2]

    enum: [0, 1, 2]

    default: 0

    description:

      The MIO bank number in which the command and data lines are configured.

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml

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@@ -39,6 +39,7 @@ properties: 
              - fsl,imx8mn-usdhc

              - fsl,imx8mp-usdhc

              - fsl,imx8mq-usdhc

              - fsl,imx8qm-usdhc

              - fsl,imx8qxp-usdhc

          - const: fsl,imx7d-usdhc

Documentation/devicetree/bindings/mmc/mtk-sd.txt

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* MTK MMC controller



The MTK  MSDC can act as a MMC controller

to support MMC, SD, and SDIO types of memory cards.



This file documents differences between the core properties in mmc.txt

and the properties used by the msdc driver.



Required properties:

- compatible: value should be either of the following.

	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135

	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173

	"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183

	"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516

	"mediatek,mt6779-mmc": for mmc host ip compatible with mt6779

	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701

	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712

	"mediatek,mt7622-mmc": for MT7622 SoC

	"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC

	"mediatek,mt7620-mmc", for MT7621 SoC (and others)



- reg: physical base address of the controller and length

- interrupts: Should contain MSDC interrupt number

- clocks: Should contain phandle for the clock feeding the MMC controller

- clock-names: Should contain the following:

	"source" - source clock (required)

	"hclk" - HCLK which used for host (required)

	"source_cg" - independent source clock gate (required for MT2712)

	"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)

- pinctrl-names: should be "default", "state_uhs"

- pinctrl-0: should contain default/high speed pin ctrl

- pinctrl-1: should contain uhs mode pin ctrl

- vmmc-supply: power to the Core

- vqmmc-supply: power to the IO



Optional properties:

- assigned-clocks: PLL of the source clock

- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock

- hs400-ds-delay: HS400 DS delay setting

- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.

				This field has total 32 stages.

				The value is an integer from 0 to 31.

- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting

				This field has total 32 stages.

				The value is an integer from 0 to 31.

- mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection

				       If present,HS400 command responses are sampled on rising edges.

				       If not present,HS400 command responses are sampled on falling edges.

- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc

		     error caused by stop clock(fifo full)

		     Valid range = [0:0x7]. if not present, default value is 0.

		     applied to compatible "mediatek,mt2701-mmc".

- resets: Phandle and reset specifier pair to softreset line of MSDC IP.

- reset-names: Should be "hrst".



Examples:

mmc0: mmc@11230000 {

	compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";

	reg = <0 0x11230000 0 0x108>;

	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;

	vmmc-supply = <&mt6397_vemc_3v3_reg>;

	vqmmc-supply = <&mt6397_vio18_reg>;

	clocks = <&pericfg CLK_PERI_MSDC30_0>,

	         <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

	clock-names = "source", "hclk";

	pinctrl-names = "default", "state_uhs";

	pinctrl-0 = <&mmc0_pins_default>;

	pinctrl-1 = <&mmc0_pins_uhs>;

	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;

	hs400-ds-delay = <0x14015>;

	mediatek,hs200-cmd-int-delay = <26>;

	mediatek,hs400-cmd-int-delay = <14>;

	mediatek,hs400-cmd-resp-sel-rising;

};

Documentation/devicetree/bindings/mmc/mtk-sd.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MTK MSDC Storage Host Controller Binding



maintainers:

  - Chaotian Jing <chaotian.jing@mediatek.com>

  - Wenbin Mei <wenbin.mei@mediatek.com>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    oneOf:

      - enum:

          - mediatek,mt2701-mmc

          - mediatek,mt2712-mmc

          - mediatek,mt6779-mmc

          - mediatek,mt7620-mmc

          - mediatek,mt7622-mmc

          - mediatek,mt8135-mmc

          - mediatek,mt8173-mmc

          - mediatek,mt8183-mmc

          - mediatek,mt8516-mmc

      - items:

          - const: mediatek,mt7623-mmc

          - const: mediatek,mt2701-mmc

      - items:

          - const: mediatek,mt8192-mmc

          - const: mediatek,mt8183-mmc



  clocks:

    description:

      Should contain phandle for the clock feeding the MMC controller.

    minItems: 2

    maxItems: 8

    items:

      - description: source clock (required).

      - description: HCLK which used for host (required).

      - description: independent source clock gate (required for MT2712).

      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).

      - description: msdc subsys clock gate (required for MT8192).

      - description: peripheral bus clock gate (required for MT8192).

      - description: AXI bus clock gate (required for MT8192).

      - description: AHB bus clock gate (required for MT8192).



  clock-names:

    minItems: 2

    maxItems: 8

    items:

      - const: source

      - const: hclk

      - const: source_cg

      - const: bus_clk

      - const: sys_cg

      - const: pclk_cg

      - const: axi_cg

      - const: ahb_cg



  pinctrl-names:

    items:

      - const: default

      - const: state_uhs



  pinctrl-0:

    description:

      should contain default/high speed pin ctrl.

    maxItems: 1



  pinctrl-1:

    description:

      should contain uhs mode pin ctrl.

    maxItems: 1



  assigned-clocks:

    description:

      PLL of the source clock.

    maxItems: 1



  assigned-clock-parents:

    description:

      parent of source clock, used for HS400 mode to get 400Mhz source clock.

    maxItems: 1



  hs400-ds-delay:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      HS400 DS delay setting.

    minimum: 0

    maximum: 0xffffffff



  mediatek,hs200-cmd-int-delay:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      HS200 command internal delay setting.

      This field has total 32 stages.

      The value is an integer from 0 to 31.

    minimum: 0

    maximum: 31



  mediatek,hs400-cmd-int-delay:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      HS400 command internal delay setting.

      This field has total 32 stages.

      The value is an integer from 0 to 31.

    minimum: 0

    maximum: 31



  mediatek,hs400-cmd-resp-sel-rising:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

      HS400 command response sample selection.

      If present, HS400 command responses are sampled on rising edges.

      If not present, HS400 command responses are sampled on falling edges.



  mediatek,latch-ck:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid

      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].

      if not present, default value is 0.

      applied to compatible "mediatek,mt2701-mmc".

    minimum: 0

    maximum: 7



  resets:

    maxItems: 1



  reset-names:

    const: hrst



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - pinctrl-names

  - pinctrl-0

  - pinctrl-1

  - vmmc-supply

  - vqmmc-supply



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/mt8173-clk.h>

    mmc0: mmc@11230000 {

        compatible = "mediatek,mt8173-mmc";

        reg = <0x11230000 0x1000>;

        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;

        vmmc-supply = <&mt6397_vemc_3v3_reg>;

        vqmmc-supply = <&mt6397_vio18_reg>;

        clocks = <&pericfg CLK_PERI_MSDC30_0>,

                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

        clock-names = "source", "hclk";

        pinctrl-names = "default", "state_uhs";

        pinctrl-0 = <&mmc0_pins_default>;

        pinctrl-1 = <&mmc0_pins_uhs>;

        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;

        hs400-ds-delay = <0x14015>;

        mediatek,hs200-cmd-int-delay = <26>;

        mediatek,hs400-cmd-int-delay = <14>;

        mediatek,hs400-cmd-resp-sel-rising;

    };



...

Documentation/devicetree/bindings/mmc/owl-mmc.yaml

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@@ -17,7 +17,9 @@ properties: 
    oneOf:

      - const: actions,owl-mmc

      - items:

          - const: actions,s700-mmc

          - enum:

              - actions,s500-mmc

              - actions,s700-mmc

          - const: actions,owl-mmc



  reg:

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