Commit cd8ca300 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner',... 

Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next

 - S2RAM support for Marvell mvebu periph clks

* clk-mvebu-periph-pm:
  clk: mvebu: armada-37xx-periph: add suspend/resume support
  clk: mvebu: armada-37xx-periph: save the IP base address in the driver data

* clk-meson:
  clk: meson: meson8b: use the regmap in the internal reset controller
  clk: meson: meson8b: register the clock controller early
  clk: meson-axg: pcie: drop the mpll3 clock parent
  clk: meson: axg: round audio system master clocks down
  clk: meson: clk-pll: drop hard-coded rates from pll tables
  clk: meson: clk-pll: remove od parameters
  clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
  clk: meson: clk-pll: add enable bit

* clk-allwinner:
  dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
  clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
  clk: sunxi-ng: a64: Add minimal rate for video PLLs
  clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
  clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
  clk: sunxi-ng: nkmp: Add constraint for maximum rate
  clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
  clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
  clk: sunxi-ng: Add maximum rate constraint to NM PLLs
  clk: sunxi-ng: h6: fix PWM gate/reset offset
  clk: sunxi-ng: h6: fix bus clocks' divider position

* clk-mvebu-dup:
  clk: mvebu: ap806: Remove superfluous of_clk_add_provider

* clk-davinci:
  clk: davinci: kill davinci_clk_reset_assert/deassert()
parents 5d3a48fe 5beb1e60 148edd50 e15d598b 6ffeddd6 e3aaadb0

arch/arm/mach-davinci/include/mach/clock.h

deleted100644 → 0
+0 −21
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-davinci/include/mach/clock.h

 *

 * Clock control driver for DaVinci - header file

 *

 * Authors: Vladimir Barinov <source@mvista.com>

 *

 * 2007 (c) MontaVista Software, Inc. This file is licensed under

 * the terms of the GNU General Public License version 2. This program

 * is licensed "as is" without any warranty of any kind, whether express

 * or implied.

 */

#ifndef __ASM_ARCH_DAVINCI_CLOCK_H

#define __ASM_ARCH_DAVINCI_CLOCK_H



struct clk;



int davinci_clk_reset_assert(struct clk *c);

int davinci_clk_reset_deassert(struct clk *c);



#endif

drivers/clk/davinci/psc.c

+0 −18
Original line number Diff line number Diff line
@@ -303,24 +303,6 @@ static int davinci_lpsc_clk_reset(struct clk *clk, bool reset) 
	return 0;

}



/*

 * REVISIT: These exported functions can be removed after a non-DT lookup is

 * added to the reset controller framework and the davinci-rproc driver is

 * updated to use the generic reset controller framework.

 */



int davinci_clk_reset_assert(struct clk *clk)

{

	return davinci_lpsc_clk_reset(clk, true);

}

EXPORT_SYMBOL(davinci_clk_reset_assert);



int davinci_clk_reset_deassert(struct clk *clk)

{

	return davinci_lpsc_clk_reset(clk, false);

}

EXPORT_SYMBOL(davinci_clk_reset_deassert);



static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,

				    unsigned long id)

{

drivers/clk/meson/axg-audio.c

+23 −11
Original line number Diff line number Diff line
@@ -101,10 +101,16 @@ static const char * const mst_mux_parent_names[] = { 
	"axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",

};



#define AXG_MST_MCLK_MUX(_name, _reg)					\

	AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \

#define AXG_MST_MUX(_name, _reg, _flag)				\

	AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,		\

		    mst_mux_parent_names, CLK_SET_RATE_PARENT)



#define AXG_MST_MCLK_MUX(_name, _reg)				\

	AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)



#define AXG_MST_SYS_MUX(_name, _reg)				\

	AXG_MST_MUX(_name, _reg, 0)



static AXG_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);

static AXG_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);

static AXG_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
@@ -112,14 +118,20 @@ static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); 
static AXG_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);

static AXG_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);

static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);

static AXG_MST_MCLK_MUX(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);

static AXG_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);

static AXG_MST_MCLK_MUX(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);

static AXG_MST_SYS_MUX(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);

static AXG_MST_SYS_MUX(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);



#define AXG_MST_MCLK_DIV(_name, _reg)					\

	AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \

#define AXG_MST_DIV(_name, _reg, _flag)				\

	AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag,		\

		    "axg_"#_name"_sel", CLK_SET_RATE_PARENT)	\



#define AXG_MST_MCLK_DIV(_name, _reg)				\

	AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)



#define AXG_MST_SYS_DIV(_name, _reg)				\

	AXG_MST_DIV(_name, _reg, 0)



static AXG_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);

static AXG_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);

static AXG_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
@@ -127,9 +139,9 @@ static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); 
static AXG_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);

static AXG_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);

static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);

static AXG_MST_MCLK_DIV(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);

static AXG_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);

static AXG_MST_MCLK_DIV(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);

static AXG_MST_SYS_DIV(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);

static AXG_MST_SYS_DIV(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);



#define AXG_MST_MCLK_GATE(_name, _reg)				\

	AXG_AUD_GATE(_name, _reg, 31,  "axg_"#_name"_div",	\

drivers/clk/meson/axg.c

+189 −143
Original line number Diff line number Diff line
@@ -22,8 +22,13 @@ 


static DEFINE_SPINLOCK(meson_clk_lock);



static struct clk_regmap axg_fixed_pll = {

static struct clk_regmap axg_fixed_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 30,

			.width   = 1,

		},

		.m = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 0,
@@ -34,11 +39,6 @@ static struct clk_regmap axg_fixed_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_MPLL_CNTL2,

			.shift   = 0,
@@ -56,15 +56,39 @@ static struct clk_regmap axg_fixed_pll = { 
		},

	},

	.hw.init = &(struct clk_init_data){

		.name = "fixed_pll",

		.name = "fixed_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_sys_pll = {

static struct clk_regmap axg_fixed_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_MPLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "fixed_pll",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_names = (const char *[]){ "fixed_pll_dco" },

		.num_parents = 1,

		/*

		 * This clock won't ever change at runtime so

		 * CLK_SET_RATE_PARENT is not required

		 */

	},

};



static struct clk_regmap axg_sys_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_SYS_PLL_CNTL,

			.shift   = 30,

			.width   = 1,

		},

		.m = {

			.reg_off = HHI_SYS_PLL_CNTL,

			.shift   = 0,
@@ -75,11 +99,6 @@ static struct clk_regmap axg_sys_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_SYS_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.l = {

			.reg_off = HHI_SYS_PLL_CNTL,

			.shift   = 31,
@@ -92,102 +111,59 @@ static struct clk_regmap axg_sys_pll = { 
		},

	},

	.hw.init = &(struct clk_init_data){

		.name = "sys_pll",

		.name = "sys_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

		.flags = CLK_GET_RATE_NOCACHE,

	},

};



static const struct pll_rate_table axg_gp0_pll_rate_table[] = {

	PLL_RATE(240000000, 40, 1, 2),

	PLL_RATE(246000000, 41, 1, 2),

	PLL_RATE(252000000, 42, 1, 2),

	PLL_RATE(258000000, 43, 1, 2),

	PLL_RATE(264000000, 44, 1, 2),

	PLL_RATE(270000000, 45, 1, 2),

	PLL_RATE(276000000, 46, 1, 2),

	PLL_RATE(282000000, 47, 1, 2),

	PLL_RATE(288000000, 48, 1, 2),

	PLL_RATE(294000000, 49, 1, 2),

	PLL_RATE(300000000, 50, 1, 2),

	PLL_RATE(306000000, 51, 1, 2),

	PLL_RATE(312000000, 52, 1, 2),

	PLL_RATE(318000000, 53, 1, 2),

	PLL_RATE(324000000, 54, 1, 2),

	PLL_RATE(330000000, 55, 1, 2),

	PLL_RATE(336000000, 56, 1, 2),

	PLL_RATE(342000000, 57, 1, 2),

	PLL_RATE(348000000, 58, 1, 2),

	PLL_RATE(354000000, 59, 1, 2),

	PLL_RATE(360000000, 60, 1, 2),

	PLL_RATE(366000000, 61, 1, 2),

	PLL_RATE(372000000, 62, 1, 2),

	PLL_RATE(378000000, 63, 1, 2),

	PLL_RATE(384000000, 64, 1, 2),

	PLL_RATE(390000000, 65, 1, 3),

	PLL_RATE(396000000, 66, 1, 3),

	PLL_RATE(402000000, 67, 1, 3),

	PLL_RATE(408000000, 68, 1, 3),

	PLL_RATE(480000000, 40, 1, 1),

	PLL_RATE(492000000, 41, 1, 1),

	PLL_RATE(504000000, 42, 1, 1),

	PLL_RATE(516000000, 43, 1, 1),

	PLL_RATE(528000000, 44, 1, 1),

	PLL_RATE(540000000, 45, 1, 1),

	PLL_RATE(552000000, 46, 1, 1),

	PLL_RATE(564000000, 47, 1, 1),

	PLL_RATE(576000000, 48, 1, 1),

	PLL_RATE(588000000, 49, 1, 1),

	PLL_RATE(600000000, 50, 1, 1),

	PLL_RATE(612000000, 51, 1, 1),

	PLL_RATE(624000000, 52, 1, 1),

	PLL_RATE(636000000, 53, 1, 1),

	PLL_RATE(648000000, 54, 1, 1),

	PLL_RATE(660000000, 55, 1, 1),

	PLL_RATE(672000000, 56, 1, 1),

	PLL_RATE(684000000, 57, 1, 1),

	PLL_RATE(696000000, 58, 1, 1),

	PLL_RATE(708000000, 59, 1, 1),

	PLL_RATE(720000000, 60, 1, 1),

	PLL_RATE(732000000, 61, 1, 1),

	PLL_RATE(744000000, 62, 1, 1),

	PLL_RATE(756000000, 63, 1, 1),

	PLL_RATE(768000000, 64, 1, 1),

	PLL_RATE(780000000, 65, 1, 1),

	PLL_RATE(792000000, 66, 1, 1),

	PLL_RATE(804000000, 67, 1, 1),

	PLL_RATE(816000000, 68, 1, 1),

	PLL_RATE(960000000, 40, 1, 0),

	PLL_RATE(984000000, 41, 1, 0),

	PLL_RATE(1008000000, 42, 1, 0),

	PLL_RATE(1032000000, 43, 1, 0),

	PLL_RATE(1056000000, 44, 1, 0),

	PLL_RATE(1080000000, 45, 1, 0),

	PLL_RATE(1104000000, 46, 1, 0),

	PLL_RATE(1128000000, 47, 1, 0),

	PLL_RATE(1152000000, 48, 1, 0),

	PLL_RATE(1176000000, 49, 1, 0),

	PLL_RATE(1200000000, 50, 1, 0),

	PLL_RATE(1224000000, 51, 1, 0),

	PLL_RATE(1248000000, 52, 1, 0),

	PLL_RATE(1272000000, 53, 1, 0),

	PLL_RATE(1296000000, 54, 1, 0),

	PLL_RATE(1320000000, 55, 1, 0),

	PLL_RATE(1344000000, 56, 1, 0),

	PLL_RATE(1368000000, 57, 1, 0),

	PLL_RATE(1392000000, 58, 1, 0),

	PLL_RATE(1416000000, 59, 1, 0),

	PLL_RATE(1440000000, 60, 1, 0),

	PLL_RATE(1464000000, 61, 1, 0),

	PLL_RATE(1488000000, 62, 1, 0),

	PLL_RATE(1512000000, 63, 1, 0),

	PLL_RATE(1536000000, 64, 1, 0),

	PLL_RATE(1560000000, 65, 1, 0),

	PLL_RATE(1584000000, 66, 1, 0),

	PLL_RATE(1608000000, 67, 1, 0),

	PLL_RATE(1632000000, 68, 1, 0),

static struct clk_regmap axg_sys_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SYS_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "sys_pll",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_names = (const char *[]){ "sys_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static const struct pll_params_table axg_gp0_pll_params_table[] = {

	PLL_PARAMS(40, 1),

	PLL_PARAMS(41, 1),

	PLL_PARAMS(42, 1),

	PLL_PARAMS(43, 1),

	PLL_PARAMS(44, 1),

	PLL_PARAMS(45, 1),

	PLL_PARAMS(46, 1),

	PLL_PARAMS(47, 1),

	PLL_PARAMS(48, 1),

	PLL_PARAMS(49, 1),

	PLL_PARAMS(50, 1),

	PLL_PARAMS(51, 1),

	PLL_PARAMS(52, 1),

	PLL_PARAMS(53, 1),

	PLL_PARAMS(54, 1),

	PLL_PARAMS(55, 1),

	PLL_PARAMS(56, 1),

	PLL_PARAMS(57, 1),

	PLL_PARAMS(58, 1),

	PLL_PARAMS(59, 1),

	PLL_PARAMS(60, 1),

	PLL_PARAMS(61, 1),

	PLL_PARAMS(62, 1),

	PLL_PARAMS(63, 1),

	PLL_PARAMS(64, 1),

	PLL_PARAMS(65, 1),

	PLL_PARAMS(66, 1),

	PLL_PARAMS(67, 1),

	PLL_PARAMS(68, 1),

	{ /* sentinel */ },

};
@@ -197,11 +173,15 @@ static const struct reg_sequence axg_gp0_init_regs[] = { 
	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x0a59a288 },

	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0xc000004d },

	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x00078000 },

	{ .reg = HHI_GP0_PLL_CNTL,	.def = 0x40010250 },

};



static struct clk_regmap axg_gp0_pll = {

static struct clk_regmap axg_gp0_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_GP0_PLL_CNTL,

			.shift   = 30,

			.width   = 1,

		},

		.m = {

			.reg_off = HHI_GP0_PLL_CNTL,

			.shift   = 0,
@@ -212,11 +192,6 @@ static struct clk_regmap axg_gp0_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_GP0_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_GP0_PLL_CNTL1,

			.shift   = 0,
@@ -232,29 +207,49 @@ static struct clk_regmap axg_gp0_pll = { 
			.shift   = 29,

			.width   = 1,

		},

		.table = axg_gp0_pll_rate_table,

		.table = axg_gp0_pll_params_table,

		.init_regs = axg_gp0_init_regs,

		.init_count = ARRAY_SIZE(axg_gp0_init_regs),

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp0_pll",

		.name = "gp0_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_gp0_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_GP0_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp0_pll",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "gp0_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static const struct reg_sequence axg_hifi_init_regs[] = {

	{ .reg = HHI_HIFI_PLL_CNTL1,	.def = 0xc084b000 },

	{ .reg = HHI_HIFI_PLL_CNTL2,	.def = 0xb75020be },

	{ .reg = HHI_HIFI_PLL_CNTL3,	.def = 0x0a6a3a88 },

	{ .reg = HHI_HIFI_PLL_CNTL4,	.def = 0xc000004d },

	{ .reg = HHI_HIFI_PLL_CNTL5,	.def = 0x00058000 },

	{ .reg = HHI_HIFI_PLL_CNTL,	.def = 0x40010250 },

};



static struct clk_regmap axg_hifi_pll = {

static struct clk_regmap axg_hifi_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_HIFI_PLL_CNTL,

			.shift   = 30,

			.width   = 1,

		},

		.m = {

			.reg_off = HHI_HIFI_PLL_CNTL,

			.shift   = 0,
@@ -265,11 +260,6 @@ static struct clk_regmap axg_hifi_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_HIFI_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_HIFI_PLL_CNTL5,

			.shift   = 0,
@@ -285,19 +275,35 @@ static struct clk_regmap axg_hifi_pll = { 
			.shift   = 29,

			.width   = 1,

		},

		.table = axg_gp0_pll_rate_table,

		.table = axg_gp0_pll_params_table,

		.init_regs = axg_hifi_init_regs,

		.init_count = ARRAY_SIZE(axg_hifi_init_regs),

		.flags = CLK_MESON_PLL_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hifi_pll",

		.name = "hifi_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_hifi_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_HIFI_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hifi_pll",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "hifi_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_fixed_factor axg_fclk_div2_div = {

	.mult = 1,

	.div = 2,
@@ -625,29 +631,31 @@ static struct clk_regmap axg_mpll3 = { 
	},

};



static const struct pll_rate_table axg_pcie_pll_rate_table[] = {

static const struct pll_params_table axg_pcie_pll_params_table[] = {

	{

		.rate	= 100000000,

		.m = 200,

		.n = 3,

		.od	= 1,

		.od2	= 3,

	},

	{ /* sentinel */ },

};



static const struct reg_sequence axg_pcie_init_regs[] = {

	{ .reg = HHI_PCIE_PLL_CNTL,	.def = 0x400106c8 },

	{ .reg = HHI_PCIE_PLL_CNTL1,	.def = 0x0084a2aa },

	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0xb75020be },

	{ .reg = HHI_PCIE_PLL_CNTL3,	.def = 0x0a47488e },

	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0xc000004d },

	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x00078000 },

	{ .reg = HHI_PCIE_PLL_CNTL6,	.def = 0x002323c6 },

	{ .reg = HHI_PCIE_PLL_CNTL,     .def = 0x400106c8 },

};



static struct clk_regmap axg_pcie_pll = {

static struct clk_regmap axg_pcie_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_PCIE_PLL_CNTL,

			.shift   = 30,

			.width   = 1,

		},

		.m = {

			.reg_off = HHI_PCIE_PLL_CNTL,

			.shift   = 0,
@@ -658,16 +666,6 @@ static struct clk_regmap axg_pcie_pll = { 
			.shift   = 9,

			.width   = 5,

		},

		.od = {

			.reg_off = HHI_PCIE_PLL_CNTL,

			.shift   = 16,

			.width   = 2,

		},

		.od2 = {

			.reg_off = HHI_PCIE_PLL_CNTL6,

			.shift   = 6,

			.width   = 2,

		},

		.frac = {

			.reg_off = HHI_PCIE_PLL_CNTL1,

			.shift   = 0,
@@ -683,29 +681,63 @@ static struct clk_regmap axg_pcie_pll = { 
			.shift   = 29,

			.width   = 1,

		},

		.table = axg_pcie_pll_rate_table,

		.table = axg_pcie_pll_params_table,

		.init_regs = axg_pcie_init_regs,

		.init_count = ARRAY_SIZE(axg_pcie_init_regs),

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll",

		.name = "pcie_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.num_parents = 1,

	},

};



static struct clk_regmap axg_pcie_pll_od = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_PCIE_PLL_CNTL,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll_od",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "pcie_pll_dco" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap axg_pcie_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_PCIE_PLL_CNTL6,

		.shift = 6,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "pcie_pll_od" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap axg_pcie_mux = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_PCIE_PLL_CNTL6,

		.mask = 0x1,

		.shift = 2,

		/* skip the parent mpll3, reserved for debug */

		.table = (u32[]){ 1 },

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_mux",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "mpll3", "pcie_pll" },

		.num_parents = 2,

		.parent_names = (const char *[]){ "pcie_pll" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -1107,6 +1139,12 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { 
		[CLKID_GEN_CLK_SEL]		= &axg_gen_clk_sel.hw,

		[CLKID_GEN_CLK_DIV]		= &axg_gen_clk_div.hw,

		[CLKID_GEN_CLK]			= &axg_gen_clk.hw,

		[CLKID_SYS_PLL_DCO]		= &axg_sys_pll_dco.hw,

		[CLKID_FIXED_PLL_DCO]		= &axg_fixed_pll_dco.hw,

		[CLKID_GP0_PLL_DCO]		= &axg_gp0_pll_dco.hw,

		[CLKID_HIFI_PLL_DCO]		= &axg_hifi_pll_dco.hw,

		[CLKID_PCIE_PLL_DCO]		= &axg_pcie_pll_dco.hw,

		[CLKID_PCIE_PLL_OD]		= &axg_pcie_pll_od.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -1185,6 +1223,8 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
	&axg_fclk_div4,

	&axg_fclk_div5,

	&axg_fclk_div7,

	&axg_pcie_pll_dco,

	&axg_pcie_pll_od,

	&axg_pcie_pll,

	&axg_pcie_mux,

	&axg_pcie_ref,
@@ -1194,6 +1234,12 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
	&axg_gen_clk_sel,

	&axg_gen_clk_div,

	&axg_gen_clk,

	&axg_fixed_pll_dco,

	&axg_sys_pll_dco,

	&axg_gp0_pll_dco,

	&axg_hifi_pll_dco,

	&axg_pcie_pll_dco,

	&axg_pcie_pll_od,

};



static const struct of_device_id clkc_match_table[] = {

drivers/clk/meson/axg.h

+7 −1
Original line number Diff line number Diff line
@@ -133,8 +133,14 @@ 
#define CLKID_PCIE_REF				78

#define CLKID_GEN_CLK_SEL			82

#define CLKID_GEN_CLK_DIV			83

#define CLKID_SYS_PLL_DCO			85

#define CLKID_FIXED_PLL_DCO			86

#define CLKID_GP0_PLL_DCO			87

#define CLKID_HIFI_PLL_DCO			88

#define CLKID_PCIE_PLL_DCO			89

#define CLKID_PCIE_PLL_OD			90



#define NR_CLKS					85

#define NR_CLKS					91



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/axg-clkc.h>

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